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| * | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
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* | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
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* | | Fix merge issuesEddie Hung2019-10-042-9/+10
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* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0411-139/+154
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0411-111/+120
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* | EnglishEddie Hung2019-10-031-3/+3
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* | More fixesEddie Hung2019-10-011-16/+16
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* | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
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* | Remove need for $currQ port connectionEddie Hung2019-09-302-111/+118
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* | Add explanation to abc_map.vEddie Hung2019-09-301-0/+16
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-308-124/+122
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| * Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
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| * synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
| | | | | | | | Fixes #1387.
* | Missing endmoduleEddie Hung2019-09-291-0/+1
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2911-21/+3006
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| * Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2911-21/+3000
| |\ | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| | * Re-orderEddie Hung2019-09-271-1/+1
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| | * TypoEddie Hung2019-09-261-1/+1
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| | * select onceEddie Hung2019-09-261-3/+5
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| | * Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-1/+3
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| | * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
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| | * Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
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| | * Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
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| | * Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
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| | * Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-233-87/+0
| | | | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405.
| | * Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
| | | | | | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
| | * Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
| | | | | | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.
| | * Vivado does not like zero width port connectionsEddie Hung2019-09-231-2/+2
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| | * Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
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| | * Add a xilinx_finalise passEddie Hung2019-09-233-0/+87
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| | * GrammarEddie Hung2019-09-201-1/+1
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| | * Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-1/+1
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| | * Tidy up, fix undrivenEddie Hung2019-09-191-32/+34
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| | * $__ABC_REG to have WIDTH parameterEddie Hung2019-09-192-17/+18
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| | * Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-194-349/+363
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| | * Revert "Different approach to timing"Eddie Hung2019-09-194-195/+405
| | | | | | | | | | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044.
| | * Different approach to timingEddie Hung2019-09-194-405/+195
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| | * Suppress $anyseq warningsEddie Hung2019-09-191-15/+32
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| | * Use (* techmap_autopurge *) to suppress techmap warningsEddie Hung2019-09-192-94/+99
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| | * D is 25 bits not 24 bits wideEddie Hung2019-09-191-1/+1
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| | * Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-198-90/+502
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| | * | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2Eddie Hung2019-09-191-1/+4
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| | * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-187-941/+19252
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| | * | | Fix copy-pasteEddie Hung2019-09-181-2/+2
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| | * | | Mis-spellEddie Hung2019-09-181-10/+25
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| | * | | Add pattern detection support for DSP48E1 model, check against vendorEddie Hung2019-09-183-8/+102
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| | * | | Add `undef DSP48E1_INSTEddie Hung2019-09-131-4/+5
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| | * | | Fix D -> P{,COUT} delayEddie Hung2019-09-131-43/+43
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| | * | | Add no MULT no DPORT configEddie Hung2019-09-134-226/+471
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| | * | | Add support for MULT and DPORTEddie Hung2019-09-134-10/+588
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