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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-205-24/+39
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| * Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-204-16/+19
| |\ | | | | | | [WIP] synth xilinx renaming, as per #1184
| | * Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-203-6/+6
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| | * | Update Makefile tooEddie Hung2019-07-181-2/+2
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| | * | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17
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| * | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
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| * | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
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* | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-151-1/+5
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| * | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Add assign PCOUT = P to DSP48E1Eddie Hung2019-08-131-0/+2
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* | | | Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-131-1/+1
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* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-1/+1
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| * | stoi -> atoiEddie Hung2019-08-071-1/+1
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* | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
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* | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
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* | | Combine techmap callsEddie Hung2019-08-081-2/+1
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* | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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* | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
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* | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
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* | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-012-5/+5
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| * | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add paramsEddie Hung2019-07-181-0/+6
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* | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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* | Make all operands signedEddie Hung2019-07-171-1/+1
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* | Update commentEddie Hung2019-07-171-5/+3
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* | SignednessEddie Hung2019-07-162-8/+8
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* | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-163-5/+9
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| * | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
* | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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* | | Oops forgot these filesEddie Hung2019-07-152-0/+5
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* | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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* | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1511-14/+604
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| * Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
| |\ | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| | * synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ | | | | | | ISE/Vivado.
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