| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | | | Make cells.box whiteboxes not blackboxes | Eddie Hung | 2019-04-16 | 1 | -2/+2 | |
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| * | | | | | | | read_verilog cells_box.v before techmap | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
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| * | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.v | Eddie Hung | 2019-04-16 | 1 | -0/+1 | |
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| * | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxes | Eddie Hung | 2019-04-16 | 2 | -0/+11 | |
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| * | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells" | Eddie Hung | 2019-04-16 | 1 | -2/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec. | |||||
| * | | | | | | | Add abc_box_id attribute to MUXF7/F8 cells | Eddie Hung | 2019-04-15 | 1 | -0/+2 | |
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| * | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-15 | 3 | -41/+60 | |
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| | * | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 1 | -1/+9 | |
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| | * | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | | | | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | | | | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 | |
| | | |_|_|/ | |/| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | | | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
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| * | | | | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
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| * | | | | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
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| * | | | | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
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| * | | | | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 2 | -30/+35 | |
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| * | | | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 | |
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| * | | | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 | |
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| * | | | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 | |
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| * | | | | | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 | |
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| * | | | | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 | |
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| * | | | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
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| * | | | | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 | |
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| * | | | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 | |
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| * | | | | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 | |
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| * | | | | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 | |
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| * | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 | |
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| * | | | | | Add delays to cells.box | Eddie Hung | 2019-04-09 | 1 | -4/+12 | |
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| * | | | | | synth_xilinx with abc9 to use -box | Eddie Hung | 2019-04-09 | 1 | -1/+4 | |
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| * | | | | | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 2 | -0/+6 | |
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| * | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-09 | 1 | -1/+9 | |
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| * | | / | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 2 | -25/+31 | |
| | |_|/ |/| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
| | |/ |/| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #842 from litghost/merge_upstream | Clifford Wolf | 2019-03-05 | 10 | -176/+570 | |
| |\ \ | | | | | | | Changes required for VPR place and route in synth_xilinx | |||||
| | * | | Revert BRAM WRITE_MODE changes. | Keith Rothman | 2019-03-04 | 1 | -12/+12 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | Revert FF models to include IS_x_INVERTED parameters. | Keith Rothman | 2019-03-01 | 1 | -6/+34 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | Use singular for disabling of DRAM or BRAM inference. | Keith Rothman | 2019-03-01 | 1 | -13/+13 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | Modify arguments to match existing style. | Keith Rothman | 2019-03-01 | 1 | -6/+6 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 11 | -221/+587 | |
| | |/ | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * / | Use "write_edif -pvector bra" for Xilinx EDIF files | Clifford Wolf | 2019-03-05 | 1 | -1/+1 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | Add support for Xilinx PS7 block | Eddie Hung | 2018-11-10 | 2 | -0/+624 | |
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| * | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. | Tim 'mithro' Ansell | 2018-10-08 | 1 | -3/+2 | |
| | | | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs. | |||||
| * | Add inout ports to cells_xtra.v | Clifford Wolf | 2018-10-04 | 2 | -2/+14 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | xilinx: Adding missing inout IO port to IOBUF | Tim Ansell | 2018-10-03 | 1 | -0/+1 | |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 | |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 2 | -3/+36 | |
| | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | |||||
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 1 | -8/+8 | |
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| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 4 | -23/+30 | |
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| * | Add techlibs/xilinx/lut2lut.v | Clifford Wolf | 2017-07-10 | 2 | -0/+66 | |
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index : iCE40/yosys | |
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