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* DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | Signed-off-by: David Shah <dave@ds0.me>
* DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-012-5/+5
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| * RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add paramsEddie Hung2019-07-181-0/+6
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* | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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* | Make all operands signedEddie Hung2019-07-171-1/+1
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* | Update commentEddie Hung2019-07-171-5/+3
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* | SignednessEddie Hung2019-07-162-8/+8
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* | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-163-5/+9
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| * | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
* | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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* | | Oops forgot these filesEddie Hung2019-07-152-0/+5
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* | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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* | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1511-14/+604
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| * Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
| |\ | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| | * synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ | | | | | | ISE/Vivado.
* | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-104-45/+42
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-102-100/+182
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| * Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-101-5/+8
| |\ | | | | | | Error out if -abc9 and -retime specified
| | * Error out if -abc9 and -retime specifiedEddie Hung2019-07-101-5/+8
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| * | Add some spacingEddie Hung2019-07-101-9/+9
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| * | Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
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| * | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
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| * | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
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| * | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
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| * | Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
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| * | Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
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| * | Fix typo and commentsEddie Hung2019-07-091-4/+4
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| * | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-091-19/+25
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| | * Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanupEddie Hung2019-07-021-0/+2
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| | * | Cleanup SRL inference/make more consistentEddie Hung2019-06-291-19/+25
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| * | | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
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| * | | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| | | | | | | | | | | | | | | | This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.
| * | | Fix spacingEddie Hung2019-07-091-1/+1
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| * | | Fix spacingEddie Hung2019-07-091-1/+1
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| * | | Decompose mux inputs in delay-orientated (rather than area) fashionEddie Hung2019-07-081-18/+30
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| * | | Do not call opt -mux_undef (part of -full) before muxcoverEddie Hung2019-07-081-1/+5
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| * | | Add one more commentEddie Hung2019-07-081-0/+3
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