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* xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
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* xilinx: add delays to INVEddie Hung2020-02-271-0/+3
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* Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
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* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-273-530/+496
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* abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
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* Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
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* Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
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* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
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* Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
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* Fix commented out specify statementEddie Hung2020-02-271-6/+6
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* xilinx: improve specify functionalityEddie Hung2020-02-275-446/+519
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* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
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* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-277-426/+151
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* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
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* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-4/+85
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* xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
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* abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-131-11/+12
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* abc9: cleanupEddie Hung2020-02-101-40/+40
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* Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-074-27/+22
| | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-53/+152
| | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
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* xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-073-1/+39
| | | | Part of #1550
* Fix $lcu -> MUXCY mapping, credit @mwkmwkmwkEddie Hung2020-02-061-4/+5
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* Fix/cleanup +/xilinx/arith_map.vEddie Hung2020-02-061-111/+44
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* Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-055-142/+375
|\ | | | | abc9: add support for required times
| * Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-273-126/+89
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| * \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-151-1/+1
| |\ \ | | | | | | | | | | | | eddie/abc9_required
| * | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-141-12/+45
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| * | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-142-13/+20
| |\ \ \ | | | | | | | | | | | | | | | eddie/abc9_required
| * \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-121-1/+0
| |\ \ \ \ | | | | | | | | | | | | | | | | | | eddie/abc9_required
| | * | | | Fix abc9_xc7.box commentsEddie Hung2020-01-071-7/+14
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| | * | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-076-155/+645
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| | * | | | | Re-enable &mfs for synth_{ecp5,xilinx}Eddie Hung2020-01-061-1/+0
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| * | | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
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| * | | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attrEddie Hung2020-01-101-61/+0
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| * | | | | | Add abc9_ops -check, -prep_times, -write_box for required timesEddie Hung2020-01-101-0/+5
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| * | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-085-1676/+518
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-066-498/+1003
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | xaig_arrival_required
| * | | | | | | | ConsistencyEddie Hung2019-12-271-1/+1
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| * | | | | | | | Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-273-24/+220
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* | | | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
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* | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read portsMarcin Kościelnicki2020-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files).
* | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
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* | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
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* | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
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* | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-281-62/+37
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| * | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-62/+37
| | |_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Now done in read_aiger
* | | | | | | | | Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
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* | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
|\ \ \ \ \ \ \ \ \ | |/ / / / / / / / |/| | | | | | | | synth_xilinx: error out if tristate without '-iopad'
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