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| * | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-012-5/+5
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| * | | | | | | | | | Add paramsEddie Hung2019-07-181-0/+6
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| * | | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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| * | | | | | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
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| * | | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
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| * | | | | | | | | | SignednessEddie Hung2019-07-162-8/+8
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| * | | | | | | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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| * | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-163-5/+9
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| | * | | | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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| * | | | | | | | | | | Oops forgot these filesEddie Hung2019-07-152-0/+5
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| * | | | | | | | | | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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| * | | | | | | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1511-14/+604
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| * | | | | | | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-104-45/+42
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| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-102-100/+182
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| * | | | | | | | | | | | xc7: Map combinational DSP48E1sDavid Shah2019-07-083-5/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | Fix box nameEddie Hung2019-09-271-1/+1
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* | | | | | | | | | | | | Missing an '&'Eddie Hung2019-09-261-1/+1
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* | | | | | | | | | | | Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-198-90/+502
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* | | | | | | | | | | xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-157-1024/+19252
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* | | | | | | | | | synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Kościelnicki2019-09-075-53/+219
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* | | | | | | | | Resolve TODO with pin assignments for SRL*Eddie Hung2019-09-041-4/+2
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* | | | | | | | | Add commentsEddie Hung2019-09-021-1/+9
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* | | | | | | | | Remove trailing spaceEddie Hung2019-08-301-2/+2
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* | | | | | | | | Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-15/+22
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-287-194/+623
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| * \ \ \ \ \ \ \ \ Merge branch 'master' into eddie/xilinx_srlEddie Hung2019-08-261-0/+8
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| * | | | | | | | | | xilinx_srl now copes with word-level flops $dff{,e}Eddie Hung2019-08-231-8/+3
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-231-8/+16
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| * | | | | | | | | | | Add variable length support to xilinx_srlEddie Hung2019-08-211-4/+3
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| * | | | | | | | | | | abc9 to perform new 'map_ffs' before 'map_luts'Eddie Hung2019-08-211-3/+18
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| * | | | | | | | | | | Add init supportEddie Hung2019-08-211-1/+1
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* | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-287-195/+653
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| * | | | | | | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
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| * | | | | | | | | xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1331.
| * | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-261-0/+8
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| | * | | | | | | | Add undocumented featureEddie Hung2019-08-231-0/+8
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| * | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| * | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-11/+22
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| * \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-235-30/+39
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| * | | | | | | | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
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| * | | | | | | | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
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| * | | | | | | | | review fixesMarcin Kościelnicki2019-08-131-18/+27
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| * | | | | | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
| | |_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | | | | | | | Put attributes above portEddie Hung2019-08-232-27/+62
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