iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Various cleanups in synth_xilinx command	Clifford Wolf	2015-01-13	1	-54/+8
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*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08	2	-38/+10
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*	added minimalistic xilinx sim models	Clifford Wolf	2015-01-08	1	-0/+150
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*	More Xilinx bram cleanups	Clifford Wolf	2015-01-07	1	-14/+14
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*	Cleanups in xilinx bram descriptions	Clifford Wolf	2015-01-07	2	-36/+36
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*	Xilinx RAMB36/RAMB18 memory_bram support complete	Clifford Wolf	2015-01-06	3	-16/+320
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	3	-24/+65
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*	small fix in xilinx/brams.v	Clifford Wolf	2015-01-06	1	-5/+5
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	4	-25/+176
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*	Various small improvements to synth_xilinx	Clifford Wolf	2015-01-06	1	-8/+6
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	2	-13/+41
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	3	-6/+10
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-05	7	-19/+172
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-04	3	-13/+182
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*	Progress in memory_bram	Clifford Wolf	2015-01-03	1	-0/+3
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*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02	1	-1/+1
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*	New $mem simlib model	Clifford Wolf	2015-01-02	1	-95/+36
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*	Progress in memory_bram	Clifford Wolf	2014-12-31	1	-3/+3
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*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31	1	-0/+20
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*	Fixed simlib entries for $memrd and $memwr	Clifford Wolf	2014-12-30	1	-0/+2
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*	Fixed build with SMALL=1	Clifford Wolf	2014-12-30	1	-0/+2
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*	Improvements in simplemap api, added $ne $nex $eq $eqx support	Clifford Wolf	2014-12-24	1	-49/+5
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*	Removed UTF-8 chars from techmap.v	Clifford Wolf	2014-12-12	1	-1/+1
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*	Added $dffe cell type	Clifford Wolf	2014-12-08	2	-1/+20
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*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08	1	-0/+32
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*	Added "abc" label in synth script	Clifford Wolf	2014-10-31	1	-6/+12
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*	Added "opt -full" alias for all more aggressive optimizations	Clifford Wolf	2014-10-31	1	-2/+6
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*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-0/+6
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*	namespace Yosys	Clifford Wolf	2014-09-27	2	-2/+10
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*	Improvements in "synth" script	Clifford Wolf	2014-09-18	1	-8/+12
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*	Fixed $macc simlib model for zero-config	Clifford Wolf	2014-09-16	1	-1/+1
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*	Added "synth" command	Clifford Wolf	2014-09-14	2	-0/+154
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*	Using alumacc in techmap.v	Clifford Wolf	2014-09-14	1	-237/+33
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*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08	1	-1/+15
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*	Simplified $fa undef model	Clifford Wolf	2014-09-08	1	-1/+1
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*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08	2	-70/+73
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*	Added $lcu cell type	Clifford Wolf	2014-09-08	2	-74/+31
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08	2	-0/+28
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*	Using maccmap for $macc and $mul techmap	Clifford Wolf	2014-09-07	1	-190/+16
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	2	-2/+2
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*	Added $macc SAT model	Clifford Wolf	2014-09-06	2	-6/+6
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*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06	2	-0/+172
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	2	-34/+5
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*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02	1	-3/+6
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*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02	1	-3/+2
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*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01	1	-2/+3
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*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-0/+17
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*	Added $alu cell type	Clifford Wolf	2014-08-30	2	-3/+47
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*	Replaced $__alu CO/CS outputs with full-width CO output	Clifford Wolf	2014-08-30	1	-32/+28
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*	Using "via_celltype" in $mul carry-save-acc implementation	Clifford Wolf	2014-08-18	1	-34/+72
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