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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-31 16:53:53 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-31 16:53:53 +0100 |
| commit | 94e6b70736934bd8ebb09c7cc74cfd443bd1d9eb (patch) | |
| tree | a5f5fbfaa3989b470345b9f620a59e15f7ad4070 /techlibs | |
| parent | 1e08621e7e2c219169b3b6c5fe1d581052e4d429 (diff) | |
| download | yosys-94e6b70736934bd8ebb09c7cc74cfd443bd1d9eb.tar.gz yosys-94e6b70736934bd8ebb09c7cc74cfd443bd1d9eb.tar.bz2 yosys-94e6b70736934bd8ebb09c7cc74cfd443bd1d9eb.zip | |
Added memory_bram (not functional yet)
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/brams.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt new file mode 100644 index 000000000..03bd2b2b3 --- /dev/null +++ b/techlibs/xilinx/brams.txt @@ -0,0 +1,20 @@ + +# This is a very simplified description of the capabilities of +# the Xilinx RAMB36 core. But it is a start.. +# +bram XILINX_RAMB36_SDP32 + init 1 + abits 10 + dbits 32 + groups 2 + wports 1 0 + rports 0 1 + wenabl 2 0 + transp 0 2 + clocks 1 2 +endbram + +match XILINX_RAMB36_SDP32 + min bits 1024 +endmatch + |