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* | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1914-81/+995
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| * | Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
| |\ \ | | | | | | | | ecp5: Add support for mapping PRLD FFs
| | * | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
| | |/ | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-186-22/+389
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| * | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-184-38/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
| * | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-163-12/+301
| |\ \ | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| | * \ Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵Eddie Hung2019-12-161-2/+8
| | |\ \ | | | | | | | | | | | | | | | eddie/xilinx_lutram
| | | * | Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
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| | * | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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| | * | Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
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| | * | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
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| | * | Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
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| | * | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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| | * | Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
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| * | | Add unconditional match blocks for force RAMEddie Hung2019-12-161-4/+36
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| * | | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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| * | | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-4/+4
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| * | | Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-18/+12
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| * | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+19
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| * | | Merge pull request #1533 from dh73/bram_xilinxEddie Hung2019-12-131-6/+9
| |\ \ \ | | |/ / | |/| | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
| | * | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-5/+5
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| | * | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-121-2/+2
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| | * | Merge https://github.com/YosysHQ/yosys into bram_xilinxDiego H2019-12-1220-775/+1170
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| | * | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
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* | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1213-30/+32
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| * | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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| * | | Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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| * | | Merge pull request #1564 from ZirconiumX/intel_housekeepingDavid Shah2019-12-118-6/+6
| |\ \ \ | | | | | | | | | | Intel housekeeping
| | * | | synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
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| | * | | synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
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| * | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-094-20/+22
| |\ \ \ | | |/ / | |/| | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| | * | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
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| | * | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-1/+1
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| | * | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-092-19/+1
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| | * | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
| | | | | | | | | | | | | | | | name and attr
| | * | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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* | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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* | | | Fix commentEddie Hung2019-12-091-1/+1
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* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-067-745/+1138
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| * | | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| | | | | | | | | | | | Fixes #1225.
| * | | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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| * | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-032-112/+270
| |\ \ | | | | | | | | Gowin: add and test DFF init values
| | * | Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
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| | * | attempt to fix formattingPepijn de Vos2019-11-251-154/+154
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| | * | gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
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| * | | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
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* | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
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* | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
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* | | Remove clkpartEddie Hung2019-12-051-4/+0
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