| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added GP_RINGOSC primitive | Andrew Zonenberg | 2016-04-06 | 1 | -0/+26 |
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| * | Added GP_POR | Andrew Zonenberg | 2016-04-04 | 1 | -0/+22 |
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| * | Added GP_BANDGAP cell | Andrew Zonenberg | 2016-04-04 | 1 | -0/+9 |
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| * | Removed more debug prints | Andrew Zonenberg | 2016-04-01 | 1 | -1/+0 |
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| * | Removed forgotten debug code | Andrew Zonenberg | 2016-04-01 | 1 | -7/+1 |
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| * | Added GreenPak inverter support | Andrew Zonenberg | 2016-04-01 | 3 | -4/+13 |
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| * | Added support for inferring counters with asynchronous resets. Fixed ↵ | Andrew Zonenberg | 2016-04-01 | 1 | -51/+210 |
| | | | | | use-after-free in inference pass. | ||||
| * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-01 | 5 | -225/+153 |
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| | * | Added ScriptPass helper class for script-like passes | Clifford Wolf | 2016-03-31 | 2 | -215/+143 |
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| | * | Renamed opt_share to opt_merge | Clifford Wolf | 2016-03-31 | 1 | -2/+2 |
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| | * | Renamed opt_const to opt_expr | Clifford Wolf | 2016-03-31 | 5 | -12/+12 |
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| * | | DFFINIT is now correctly called for all kinds of flipflop, not just DFF | Andrew Zonenberg | 2016-03-31 | 1 | -0/+6 |
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| * | | Fixed incorrect port name in cells_map.v | Andrew Zonenberg | 2016-03-31 | 1 | -2/+2 |
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| * | | Fixed typo (wasn't written in 2012) | Andrew Zonenberg | 2016-03-30 | 1 | -1/+1 |
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| * | Fixed typo in greenpak4_counters.cc | Clifford Wolf | 2016-03-31 | 1 | -1/+1 |
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| * | Renamed counters pass to greenpak4_counters | Andrew Zonenberg | 2016-03-30 | 3 | -1/+290 |
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| * | Added initial implementation of "counters" pass to synth_greenpak4. Can only ↵ | Andrew Zonenberg | 2016-03-30 | 1 | -0/+2 |
| | | | | | infer non-resettable down counters for now. | ||||
| * | Updated tech lib for greenpak4 counter with some clarifications | Andrew Zonenberg | 2016-03-30 | 1 | -3/+3 |
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| * | Initial work on greenpak4 counter extraction. Doesn't work but a decent start | Andrew Zonenberg | 2016-03-30 | 1 | -0/+27 |
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| * | Added splitnets to synth_greenpak4 | Andrew Zonenberg | 2016-03-29 | 1 | -0/+2 |
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| * | Added more cell help messages | Clifford Wolf | 2016-03-29 | 1 | -0/+73 |
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| * | Fixed indenting in techlibs/greenpak4/gp_dff.lib | Clifford Wolf | 2016-03-29 | 1 | -5/+5 |
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| * | Added keep constraint to GP_SYSRESET cell | Andrew Zonenberg | 2016-03-28 | 1 | -0/+2 |
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| * | Added GP_SYSRESET block | Andrew Zonenberg | 2016-03-28 | 1 | -0/+7 |
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| * | Added GP_COUNT8/GP_COUNT14 cells | Andrew Zonenberg | 2016-03-26 | 1 | -0/+22 |
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| * | Changed GP_LFOSC parameter configuration | Andrew Zonenberg | 2016-03-26 | 1 | -1/+3 |
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| * | Added GP_LFOSC cell | Andrew Zonenberg | 2016-03-26 | 1 | -0/+17 |
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| * | Renamed GP4_V* cells to GP_V* for consistency | Andrew Zonenberg | 2016-03-26 | 1 | -2/+3 |
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| * | Added GP_DFFS, GP_DFFR, and GP_DFFSR | Clifford Wolf | 2016-03-23 | 4 | -21/+76 |
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| * | Added GP_DFF INIT parameter | Clifford Wolf | 2016-03-23 | 2 | -0/+4 |
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| * | Improvements in synth_greenpak4, added -part option | Clifford Wolf | 2016-03-21 | 1 | -30/+25 |
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| * | Added black box modules for all the 7-series design elements (as listed in ↵ | Clifford Wolf | 2016-03-19 | 4 | -0/+3441 |
| | | | | | ug953) | ||||
| * | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 | 1 | -0/+2 |
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| * | Work around DDR dout sim glitches in ice40 SB_IO sim model | Clifford Wolf | 2016-02-07 | 1 | -1/+7 |
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| * | Added dffsr2dff | Clifford Wolf | 2016-02-02 | 1 | -0/+2 |
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| * | Progress in cell library documentation | Clifford Wolf | 2016-02-01 | 1 | -0/+238 |
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| * | Added "abc -luts" option, Improved Xilinx logic mapping | Clifford Wolf | 2016-02-01 | 1 | -2/+2 |
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| * | Re-run ice40_opt in "synth_ice40 -abc2" | Clifford Wolf | 2015-12-22 | 1 | -1/+4 |
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| * | Improvements in ice40_opt | Clifford Wolf | 2015-12-22 | 1 | -5/+16 |
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| * | Bugfix in ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -2/+2 |
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| * | Improved ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -1/+22 |
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| * | Run opt_const before check in default scripts | Clifford Wolf | 2015-12-22 | 2 | -0/+4 |
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| * | Added "synth_ice40 -abc2" | Clifford Wolf | 2015-12-08 | 1 | -0/+11 |
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| * | Merge pull request #108 from cseed/master | Clifford Wolf | 2015-12-07 | 1 | -1/+3 |
| |\ | | | | | Added LO to ICESTORM_LC for LUT cascade route. | ||||
| | * | Added LO to ICESTORM_LC for LUT cascade route. | Cotton Seed | 2015-12-06 | 1 | -1/+3 |
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| * | | Added ice40_ffinit pass | Clifford Wolf | 2015-11-26 | 3 | -0/+145 |
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| * | | Fixed WE/RE usage in iCE40 BRAM mapping | Clifford Wolf | 2015-11-24 | 1 | -8/+8 |
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| * | | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling | Clifford Wolf | 2015-11-06 | 1 | -2/+2 |
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| * | | Bugfix in Xilinx LUT mapping | Clifford Wolf | 2015-10-30 | 1 | -1/+1 |
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| * | | Progress on cell help messages | Clifford Wolf | 2015-10-20 | 1 | -18/+114 |
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index : iCE40/yosys | |
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