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| author | Clifford Wolf <clifford@clifford.at> | 2016-02-01 12:40:32 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-02-01 12:40:32 +0100 |
| commit | 17372d8abde0139df4b8df3ebbeb71b222157200 (patch) | |
| tree | c817af21a34ab38aafd8690fd4fd9f6d8133ec35 /techlibs | |
| parent | 92515535924bcda6b8b9d639764ef8312467db0c (diff) | |
| download | yosys-17372d8abde0139df4b8df3ebbeb71b222157200.tar.gz yosys-17372d8abde0139df4b8df3ebbeb71b222157200.tar.bz2 yosys-17372d8abde0139df4b8df3ebbeb71b222157200.zip | |
Added "abc -luts" option, Improved Xilinx logic mapping
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index fbcc96014..6358a266b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -97,7 +97,7 @@ struct SynthXilinxPass : public Pass { log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); - log(" abc -lut 5:8 [-dff]\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log("\n"); log(" map_cells:\n"); @@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : "")); + Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); } |