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* Added "wreduce -memx"Clifford Wolf2016-08-201-2/+6
* Added memory_memx pass, "memory -memx", and "prep -memx"Clifford Wolf2016-08-191-2/+17
* Added greenpak4_dffinvClifford Wolf2016-08-153-0/+199
* greenpak4: Changed name of inverted output ports for consistencyAndrew Zonenberg2016-08-142-19/+19
* greenpak4: Added GP_DFFxI cellsAndrew Zonenberg2016-08-142-0/+68
* greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)Andrew Zonenberg2016-08-131-10/+10
* synth_greenpak4: use attrmvcp to move LOC from wires to cells.whitequark2016-08-101-0/+2
* Added $anyconst and $aconstClifford Wolf2016-07-271-0/+24
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+17
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-9/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+16
* Added GP_DAC cellAndrew Zonenberg2016-07-111-0/+8
* Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
* Removed splitnets in prep for new gp4par parserAndrew Zonenberg2016-07-111-1/+0
* Added "prep -auto-top" and "synth -auto-top"Clifford Wolf2016-07-112-6/+23
* greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
* Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiationsClifford Wolf2016-07-082-13/+24
* Improved ice40_ffinit error reportingClifford Wolf2016-06-301-1/+5
* Added "deminout"Clifford Wolf2016-06-191-0/+1
* Improved support for $sop cellsClifford Wolf2016-06-172-4/+4
* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-0/+28
* Added "nlutmap -assert"Clifford Wolf2016-06-091-3/+3
* Do not run "wreduce" in "prep -ifx"Clifford Wolf2016-06-081-2/+3
* Added "proc_mux -ifx"Clifford Wolf2016-06-061-2/+11
* Added GP_DELAY cellAndrew Zonenberg2016-05-071-0/+29
* Fixed typo in port nameAndrew Zonenberg2016-05-071-1/+1
* Fixed extra semicolonAndrew Zonenberg2016-05-071-1/+1
* Fixed typo in parameter nameAndrew Zonenberg2016-05-071-1/+1
* Added simulation timescale declarationAndrew Zonenberg2016-05-071-0/+2
* Added synth_ice40 support for latches via logic loopsClifford Wolf2016-05-063-0/+13
* Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"Clifford Wolf2016-05-061-3/+15
* Changed order of passes for better handling of INIT attributes on "output reg...Andrew Zonenberg2016-05-041-2/+2
* Renamed module parameterAndrew Zonenberg2016-05-041-4/+4
* Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cell...Andrew Zonenberg2016-05-043-18/+1
* Fixed incorrect signal naming in GP_IOBUFAndrew Zonenberg2016-05-041-2/+2
* Added tri-state I/O extraction for GreenPakAndrew Zonenberg2016-05-035-2/+29
* Added GreenPak I/O buffer cellsAndrew Zonenberg2016-05-031-0/+17
* Added comment to clarify GP_ABUF cellAndrew Zonenberg2016-05-021-0/+2
* Added GP_ABUF cellAndrew Zonenberg2016-05-021-0/+6
* Added GP_PGA cellAndrew Zonenberg2016-04-271-0/+11
* Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-242-64/+80
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| * Added "prep -flatten" and "synth -flatten"Clifford Wolf2016-04-242-7/+36
| * Converted "prep" to ScriptPassClifford Wolf2016-04-242-60/+47
* | Removed VIN_BUF_ENAndrew Zonenberg2016-04-241-1/+0
* | Renamed VOUT to OUT on GP_ACMP cellAndrew Zonenberg2016-04-231-1/+3
* | Added GP_ACMP cellAndrew Zonenberg2016-04-231-0/+12
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* Run clean after splitnets in synth_greenpak4Clifford Wolf2016-04-231-1/+1
* Merge https://github.com/azonenberg/yosysClifford Wolf2016-04-231-1/+7
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| * Fixed typoAndrew Zonenberg2016-04-221-1/+1
| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-229-12/+12
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