aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
|
* Added support for initialized xilinx bramsClifford Wolf2015-04-0610-91/+314
|
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
|
* Added Xilinx bram black-box modulesClifford Wolf2015-04-063-0/+322
|
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-051-6/+6
| | | | | | this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-051-0/+29
|
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-5/+6
|
* Fixes in cmos_cells.vClifford Wolf2015-03-251-3/+12
|
* Added very first version of "synth_ice40"Clifford Wolf2015-03-054-0/+211
|
* Added $assume cell typeClifford Wolf2015-02-261-1/+18
|
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-152-0/+4
|
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-152-7/+24
|
* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-151-2/+2
|
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-3/+15
|
* Added $meminit cell typeClifford Wolf2015-02-141-0/+22
|
* Added "check" commandClifford Wolf2015-02-131-0/+4
|
* Some test related fixesClifford Wolf2015-02-121-4/+4
| | | | (incl. removal of three bad test cases)
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
|
* no support for 6-series xilinx devicesClifford Wolf2015-02-011-1/+1
|
* Removed old XST-based xilinx examplesClifford Wolf2015-02-0111-208/+0
|
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-019-1/+84
|
* Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-011-4/+18
|
* Added "make mklibyosys", some minor API changesClifford Wolf2015-02-011-1/+9
|
* Added "fsm -encfile"Clifford Wolf2015-01-301-2/+9
|
* Fixed xilinx FDSE sim modelClifford Wolf2015-01-241-2/+2
|
* Added $equiv cell typeClifford Wolf2015-01-191-1/+23
|
* Various cleanups in xilinx techlibClifford Wolf2015-01-187-9/+110
|
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-183-468/+55
|
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-171-2/+28
|
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-174-2/+106
|
* Added cells.libClifford Wolf2015-01-162-0/+109
|
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-161-0/+2
|
* Added more FF types to xilinx/cells.vClifford Wolf2015-01-161-25/+28
|
* Fixed xilinx bram clock inverted configClifford Wolf2015-01-161-21/+35
|
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-161-116/+116
|
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-152-2/+30
|
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-131-54/+8
|
* Added add_share_file Makefile macroClifford Wolf2015-01-082-38/+10
|
* added minimalistic xilinx sim modelsClifford Wolf2015-01-081-0/+150
|
* More Xilinx bram cleanupsClifford Wolf2015-01-071-14/+14
|
* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-072-36/+36
|
* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-063-16/+320
|
* Towards Xilinx bram supportClifford Wolf2015-01-063-24/+65
|
* small fix in xilinx/brams.vClifford Wolf2015-01-061-5/+5
|
* Towards Xilinx bram supportClifford Wolf2015-01-064-25/+176
|
* Various small improvements to synth_xilinxClifford Wolf2015-01-061-8/+6
|
* Towards Xilinx bram supportClifford Wolf2015-01-062-13/+41
|
* Towards Xilinx bram supportClifford Wolf2015-01-063-6/+10
|
* Towards Xilinx bram supportClifford Wolf2015-01-057-19/+172
|
* Towards Xilinx bram supportClifford Wolf2015-01-043-13/+182
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 07:58:02 +0000