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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-12 17:45:44 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-12 17:45:44 +0100 |
| commit | d58c3eca3a6d4ab00021769fb31ee0279c2fcbab (patch) | |
| tree | 20d893fe76bc6b392e672f414720fc67295a6fdc /techlibs | |
| parent | 554a8df5e2e7c750b76021821bdf2e07970b9dbf (diff) | |
| download | yosys-d58c3eca3a6d4ab00021769fb31ee0279c2fcbab.tar.gz yosys-d58c3eca3a6d4ab00021769fb31ee0279c2fcbab.tar.bz2 yosys-d58c3eca3a6d4ab00021769fb31ee0279c2fcbab.zip | |
Some test related fixes
(incl. removal of three bad test cases)
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index d0feadd81..a73c6ee09 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1328,7 +1328,7 @@ output reg [WIDTH-1:0] Q; always @* begin if (EN == EN_POLARITY) - Q <= D; + Q = D; end endmodule @@ -1356,11 +1356,11 @@ generate for (i = 0; i < WIDTH; i = i+1) begin:bit always @* if (pos_clr[i]) - Q[i] <= 0; + Q[i] = 0; else if (pos_set[i]) - Q[i] <= 1; + Q[i] = 1; else if (pos_en) - Q[i] <= D[i]; + Q[i] = D[i]; end endgenerate |