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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0619-40/+69
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| * Valid to have attribute starting with SB_CARRY.Miodrag Milanovic2020-01-041-0/+2
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| * Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-0218-40/+67
| |\ | | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| | * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-0118-40/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | | Fix spacingEddie Hung2020-01-021-1/+1
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* | | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0214-66/+86
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| * | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-0212-37/+37
| |\ \ | | | | | | | | "abc -dff" to no longer retime by default
| | * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-3011-12/+12
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| | * | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
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| | * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-3011-13/+13
| | | | | | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
| * | | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
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| * | | Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
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| * | Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
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* | | Update commentsEddie Hung2020-01-021-11/+6
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* | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-022-58/+58
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* | | Clamp -46ps for FDPE* tooEddie Hung2020-01-011-2/+2
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* | | Restore abc9 -keepffEddie Hung2020-01-012-86/+6
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* | | Re-arrange FD orderEddie Hung2019-12-313-182/+182
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* | | Missing characterEddie Hung2019-12-311-1/+1
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* | | Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
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* | | Cleanup ice40 boxesEddie Hung2019-12-313-30/+43
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* | | Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
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* | | Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
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* | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
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* | | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
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* | | Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
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* | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3010-32/+377
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| * | Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-301-11/+6
| |\ \ | | |/ | |/| Make iopad option default for all xilinx flows
| | * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-288-10/+368
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| | * | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
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| | * | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
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| | * | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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| * | | Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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| * | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-253-3/+6
| |\ \ | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| | * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-3/+6
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| * / xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
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* | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
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* | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| * Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
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| * Revert "Optimise write_xaiger"Eddie Hung2019-12-203-15/+0
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| * Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-193-0/+15
| |\ | | | | | | Optimise write_xaiger
| | * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
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| * | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
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| * | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
| | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
* | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
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