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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 12:24:03 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-19 12:24:03 -0500 |
| commit | df626ee7abca3446225dac9179d7e7f380774b2c (patch) | |
| tree | 548ad4c0f8492421a1f06f7f659e1759a2d3c955 /techlibs | |
| parent | d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c (diff) | |
| parent | 91467938c477c5c668f5ea1a38fef59e2b19db5c (diff) | |
| download | yosys-df626ee7abca3446225dac9179d7e7f380774b2c.tar.gz yosys-df626ee7abca3446225dac9179d7e7f380774b2c.tar.bz2 yosys-df626ee7abca3446225dac9179d7e7f380774b2c.zip | |
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Optimise write_xaiger
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 5 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
3 files changed, 15 insertions, 0 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index b71bb2395..16ff9c57a 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -321,6 +321,11 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index ed7a16c08..5073ba917 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 971089b28..ff530b819 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -540,6 +540,11 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); |