iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added ice40_ffinit pass	Clifford Wolf	2015-11-26	3	-0/+145
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*	Fixed WE/RE usage in iCE40 BRAM mapping	Clifford Wolf	2015-11-24	1	-8/+8
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*	Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling	Clifford Wolf	2015-11-06	1	-2/+2
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*	Bugfix in Xilinx LUT mapping	Clifford Wolf	2015-10-30	1	-1/+1
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*	Progress on cell help messages	Clifford Wolf	2015-10-20	1	-18/+114
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*	Progress on cell help messages	Clifford Wolf	2015-10-17	2	-53/+106
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*	Added "prep" command	Clifford Wolf	2015-10-14	2	-0/+157
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*	Added more cell descriptions	Clifford Wolf	2015-10-14	1	-0/+85
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*	Added first help messages for cell types	Clifford Wolf	2015-10-14	4	-0/+292
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*	Added examples/ top-level directory	Clifford Wolf	2015-10-13	14	-279/+0
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*	Added read-enable to memory model	Clifford Wolf	2015-09-25	6	-29/+36
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*	Added nlutmap	Clifford Wolf	2015-09-18	1	-2/+2
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*	Renamed GreenPAK4 cells, improved GP4 DFF mapping	Clifford Wolf	2015-09-18	5	-9/+50
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*	Fixed copy&paste typo in synth_greenpak4	Clifford Wolf	2015-09-16	1	-3/+3
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*	Added GreenPAK4 skeleton	Clifford Wolf	2015-09-16	4	-0/+297
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*	Fixed ice40 handling of negclk RAM40	Clifford Wolf	2015-09-10	2	-12/+12
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*	Switched to Python 3	Clifford Wolf	2015-08-22	4	-10/+4
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*	Another bugfix for ice40 and xilinx brams_init make rules	Clifford Wolf	2015-08-16	4	-9/+9
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*	Fixed Makefile rules for generated share files	Clifford Wolf	2015-08-16	2	-2/+13
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*	Added $tribuf and $_TBUF_ sim models	Clifford Wolf	2015-08-16	2	-0/+20
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*	Added tribuf command	Clifford Wolf	2015-08-16	1	-0/+2
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*	Added $tribuf and $_TBUF_ cell types	Clifford Wolf	2015-08-16	1	-1/+1
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*	Another block of spelling fixes	Larry Doolittle	2015-08-14	3	-4/+4
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*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12	4	-22/+3
\| \| \| \|	This is based on work done by Larry Doolittle
*	Improved handling of "keep" attributes in hierarchical designs in opt_clean	Clifford Wolf	2015-08-12	1	-2/+1
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*	Added iCE40 WARMBOOT cell	Marcus Comstedt	2015-08-06	1	-0/+10
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*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31	1	-1/+2
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*	Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)	Clifford Wolf	2015-07-27	1	-1/+0
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*	iCE40 DFF sim models: init Q regs to 0	Clifford Wolf	2015-07-20	1	-20/+43
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*	Avoid tristate warning for blackbox ice40/cells_sim.v	Clifford Wolf	2015-07-18	1	-0/+2
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*	Improved liberty file test case	Clifford Wolf	2015-07-06	1	-1/+2
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*	Added "synth -nofsm"	Clifford Wolf	2015-07-02	1	-1/+10
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	13	-30/+30
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*	iCE40: set min bram efficiency to 2%	Clifford Wolf	2015-06-20	1	-2/+2
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*	Added "synth -nordff -noalumacc"	Clifford Wolf	2015-06-15	1	-3/+20
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*	synth_ice40 now flattens by default	Clifford Wolf	2015-06-09	1	-4/+8
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*	Added iCE40 PLL cells	Clifford Wolf	2015-05-31	1	-0/+168
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*	Added output args to synth_ice40	Clifford Wolf	2015-05-26	2	-2/+37
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*	improved ice40 SB_IO sim model	Clifford Wolf	2015-05-23	1	-16/+9
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*	Added ice40 SB_IO sim model	Clifford Wolf	2015-05-23	1	-1/+46
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*	Verific build fixes	Clifford Wolf	2015-05-17	2	-4/+4
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*	ice40_opt bugfix	Clifford Wolf	2015-04-27	2	-6/+4
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*	iCE40: SB_CARRY const fold -> unmap SB_LUT	Clifford Wolf	2015-04-27	1	-3/+44
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*	Added simplemap $lut support	Clifford Wolf	2015-04-27	1	-8/+2
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*	Added iCE40 const folding support for SB_CARRY	Clifford Wolf	2015-04-27	3	-2/+134
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*	Initialization support for all iCE40 bram modes	Clifford Wolf	2015-04-26	8	-28/+65
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*	initialized iCE40 brams (mode 0)	Clifford Wolf	2015-04-25	5	-54/+261
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*	improved iCE40 SB_RAM40_4K simulation model	Clifford Wolf	2015-04-25	1	-59/+83
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*	More iCE40 bram improvements	Clifford Wolf	2015-04-25	4	-51/+69
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*	iCE40 bram progress	Clifford Wolf	2015-04-24	2	-16/+35
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