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* Added ice40_ffinit passClifford Wolf2015-11-263-0/+145
* Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-241-8/+8
* Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-061-2/+2
* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-301-1/+1
* Progress on cell help messagesClifford Wolf2015-10-201-18/+114
* Progress on cell help messagesClifford Wolf2015-10-172-53/+106
* Added "prep" commandClifford Wolf2015-10-142-0/+157
* Added more cell descriptionsClifford Wolf2015-10-141-0/+85
* Added first help messages for cell typesClifford Wolf2015-10-144-0/+292
* Added examples/ top-level directoryClifford Wolf2015-10-1314-279/+0
* Added read-enable to memory modelClifford Wolf2015-09-256-29/+36
* Added nlutmapClifford Wolf2015-09-181-2/+2
* Renamed GreenPAK4 cells, improved GP4 DFF mappingClifford Wolf2015-09-185-9/+50
* Fixed copy&paste typo in synth_greenpak4Clifford Wolf2015-09-161-3/+3
* Added GreenPAK4 skeletonClifford Wolf2015-09-164-0/+297
* Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-102-12/+12
* Switched to Python 3Clifford Wolf2015-08-224-10/+4
* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-164-9/+9
* Fixed Makefile rules for generated share filesClifford Wolf2015-08-162-2/+13
* Added $tribuf and $_TBUF_ sim modelsClifford Wolf2015-08-162-0/+20
* Added tribuf commandClifford Wolf2015-08-161-0/+2
* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-161-1/+1
* Another block of spelling fixesLarry Doolittle2015-08-143-4/+4
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-124-22/+3
* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-121-2/+1
* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-061-0/+10
* Added WORDS parameter to $meminitClifford Wolf2015-07-311-1/+2
* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-271-1/+0
* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-201-20/+43
* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-181-0/+2
* Improved liberty file test caseClifford Wolf2015-07-061-1/+2
* Added "synth -nofsm"Clifford Wolf2015-07-021-1/+10
* Fixed trailing whitespacesClifford Wolf2015-07-0213-30/+30
* iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-201-2/+2
* Added "synth -nordff -noalumacc"Clifford Wolf2015-06-151-3/+20
* synth_ice40 now flattens by defaultClifford Wolf2015-06-091-4/+8
* Added iCE40 PLL cellsClifford Wolf2015-05-311-0/+168
* Added output args to synth_ice40Clifford Wolf2015-05-262-2/+37
* improved ice40 SB_IO sim modelClifford Wolf2015-05-231-16/+9
* Added ice40 SB_IO sim modelClifford Wolf2015-05-231-1/+46
* Verific build fixesClifford Wolf2015-05-172-4/+4
* ice40_opt bugfixClifford Wolf2015-04-272-6/+4
* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-271-3/+44
* Added simplemap $lut supportClifford Wolf2015-04-271-8/+2
* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-273-2/+134
* Initialization support for all iCE40 bram modesClifford Wolf2015-04-268-28/+65
* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-255-54/+261
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-251-59/+83
* More iCE40 bram improvementsClifford Wolf2015-04-254-51/+69
* iCE40 bram progressClifford Wolf2015-04-242-16/+35
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