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| | | * | | | | | | | | | | | | synth_xilinx: Add -nocarry and -nomux options.Marcin Koƛcielnicki2019-04-301-7/+26
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| * | | | | | | | | | | | | | | Realistic delays for RAM32X1D tooEddie Hung2019-06-251-2/+2
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| * | | | | | | | | | | | | | | Add RAM32X1D box infoEddie Hung2019-06-252-4/+12
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-255-8/+72
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| | * | | | | | | | | | | | | Add RAM32X1D supportEddie Hung2019-06-245-20/+73
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| * | | | | | | | | | | | | | Use LUT delays for dist RAM delaysEddie Hung2019-06-241-4/+4
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| * | | | | | | | | | | | | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
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| * | | | | | | | | | | | | Revert "Re-enable dist RAM boxes for ECP5"Eddie Hung2019-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ca0225fcfaa8c9c68647034351a1569464959edf.
| * | | | | | | | | | | | | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
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| * | | | | | | | | | | | | Add Xilinx dist RAM as comb boxesEddie Hung2019-06-242-0/+16
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| * | | | | | | | | | | | Add comments to ecp5 boxEddie Hung2019-06-221-0/+6
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| * | | | | | | | | | | | Add comment to xc7 boxEddie Hung2019-06-221-0/+3
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| * | | | | | | | | | | | Fix and cleanup ice40 boxes for carry in/outEddie Hung2019-06-224-313/+25
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| * | | | | | | | | | | | Carry in/out box ordering now move to end, not swap with endEddie Hung2019-06-221-12/+12
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| * | | | | | | | | | | | Remove DFF and RAMD box info for nowEddie Hung2019-06-212-36/+0
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| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-4/+5
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| | * | | | | | | | | | ecp5: Improve mapping of $alu when BI is usedDavid Shah2019-06-211-4/+5
| | | |_|_|_|_|_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-201-1/+1
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| | * | | | | | | | | Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
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| | * | | | | | | | | Fixed the help summary line for a few commandsacw12512019-06-191-1/+1
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| * | | | | | | | | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
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| * | | | | | | | | Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
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| * | | | | | | | | Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
| | |_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
| * | | | | | | | Clean upEddie Hung2019-06-181-6/+4
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| * | | | | | | | Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
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| * | | | | | | Fix copy-pasta issueEddie Hung2019-06-171-9/+8
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| * | | | | | Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
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| * | | | | | Simplify commentEddie Hung2019-06-171-1/+1
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* | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-5/+5
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| * | | | | Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
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* | | | | | Add box delays for FD*Eddie Hung2019-06-171-10/+10
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* | | | | | Merge remote-tracking branch 'origin/xaig' into xaig_dffEddie Hung2019-06-171-1/+2
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| * | | | | Try -W 300Eddie Hung2019-06-171-1/+2
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* | | | | CleanupEddie Hung2019-06-163-11/+11
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* | | | | Add +/xilinx/abc_ffEddie Hung2019-06-151-0/+33
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* | | | | Fix spacingEddie Hung2019-06-151-1/+1
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* | | | | Use $__ABC_FF_ instead of $_FF_Eddie Hung2019-06-151-2/+10
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* | | | | Re-order alphabeticallyEddie Hung2019-06-151-1/+1
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* | | | | Fix initialisation of flopsEddie Hung2019-06-152-12/+12
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* | | | | Map to $_FF_ instead of $_DFF_P_ to prevent recursion issuesEddie Hung2019-06-152-2/+2
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* | | | | Wrap FDRE with $__ABC_FDRE containing combEddie Hung2019-06-154-12/+29
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* | | / Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
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* | | As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
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* | | Resolve comments from @daveshah1Eddie Hung2019-06-141-1/+1
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* | | Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
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* | | Update delays based on SymbiFlow/prjxray-dbEddie Hung2019-06-141-12/+13
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* | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-144-3/+3
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* | | Comment out dist RAM boxing on ECP5 for nowEddie Hung2019-06-141-1/+1
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* | | Remove WIP ABC9 flop supportEddie Hung2019-06-144-46/+46
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* | | Make doc consistentEddie Hung2019-06-143-3/+6
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