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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:34:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:34:48 -0700 |
| commit | ac18a76bebad001fc3e617a7cefebe13610abcb8 (patch) | |
| tree | 64b5d42213c39d95f59602df42376f6607a6cf5f /techlibs | |
| parent | 7a3c403ba0e411c990be59da44e1decb6aafc8f8 (diff) | |
| download | yosys-ac18a76bebad001fc3e617a7cefebe13610abcb8.tar.gz yosys-ac18a76bebad001fc3e617a7cefebe13610abcb8.tar.bz2 yosys-ac18a76bebad001fc3e617a7cefebe13610abcb8.zip | |
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index ba34425d6..8688c1c3b 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -29,7 +29,7 @@ module \$_DFF_P_ (input D, C, output Q); `else wire Q_next; \$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0)); - \$_DFF_P_ abc_dff (.D(Q_next), .Q(Q), .C(C)); + \$_FF_ abc_dff (.D(Q_next), .Q(Q)); `endif endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b9da4e6a6..375ab7af1 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -277,7 +277,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_cells")) { run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); if (abc == "abc9") - run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v"); + run("techmap -D _ABC -map +/xilinx/ff_map.v t:$_DFF*"); run("clean"); } |