| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 | |
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| | | * | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 | |
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| | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 3 | -18/+36 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 29 | -299/+1059 | |
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| | * | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 | |
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| | * | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 | |
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| | * | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 | |
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| | * | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| * | | | | | | Fix spacing | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| * | | | | | | Remove unused model | Eddie Hung | 2019-08-23 | 1 | -13/+0 | |
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| * | | | | | | Put attributes above port | Eddie Hung | 2019-08-23 | 2 | -27/+62 | |
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 17 | -102/+981 | |
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| | * | | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | * | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 | |
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| | * | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 | |
| | |\ \ \ | | | | | | | | | | | Anlogic fixes and optimization | |||||
| | | * \ \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 7 | -165/+37 | |
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| | | * | | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 | |
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| | * | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 | |
| | |\ \ \ \ | | |_|_|/ | |/| | | | Initial support for Efinix Trion series FPGAs | |||||
| | | * | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
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| | | * | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 | |
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| | | * | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 | |
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| | | * | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 | |
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| | | * | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
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| | | * | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 | |
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| | | * | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 | |
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| | | * | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
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| | | * | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 9 | -267/+303 | |
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| | | * | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
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| | | * | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
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| | | * | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
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| | | * | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
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| * | | | | | | Use semicolon | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | techmap before read | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| | * | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 | |
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| * | | | | | | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 6 | -171/+26 | |
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| * | | | | | | ecp5: remove DPR16X4 from abc_unmap.v | Eddie Hung | 2019-08-20 | 1 | -20/+0 | |
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| * | | | | | | ecp5 to use -max_iter 1 | Eddie Hung | 2019-08-20 | 3 | -4/+3 | |
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| * | | | | | | ecp5 to use abc_map.v and _unmap.v | Eddie Hung | 2019-08-20 | 7 | -14/+89 | |
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| * | | | | | | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 | |
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| * | | | | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 6 | -359/+17 | |
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| * | | | | | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 | |
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| * | | | | | | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 | |
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| * | | | | | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 | |
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| * | | | | | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 | |
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index : iCE40/yosys | |
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