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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 11:47:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 11:47:06 -0700 |
| commit | 5d0f6cbd540e1be4525563329dabd2f2aaf7069e (patch) | |
| tree | 49ca0896823d9b750f8ccd370730dad82d46d21b /techlibs | |
| parent | d4d692989ae2e2b1525e376507468d5559ded162 (diff) | |
| download | yosys-5d0f6cbd540e1be4525563329dabd2f2aaf7069e.tar.gz yosys-5d0f6cbd540e1be4525563329dabd2f2aaf7069e.tar.bz2 yosys-5d0f6cbd540e1be4525563329dabd2f2aaf7069e.zip | |
techmap before read
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 263788fec..218192315 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -390,8 +390,8 @@ struct SynthXilinxPass : public ScriptPass else if (abc9) { if (family != "xc7") log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); - run("read_verilog -icells -lib +/xilinx/abc_model.v"); run("techmap -map +/xilinx/abc_map.v -max_iter 1"); + run("read_verilog -icells -lib +/xilinx/abc_model.v"); if (nowidelut) run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); else |