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* intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
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* intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
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* intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-047-19/+149
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* simcells: Fix reset polarity for $_DLATCH_???_ cells.Marcelina Kościelnicka2020-06-302-5/+5
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-2316-128/+128
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* Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-1/+1
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-233-0/+2293
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Use C++11 final/override keywords.whitequark2020-06-1831-95/+95
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* Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
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* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
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* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-2/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+1
|\ | | | | abc9: -dff improvements
| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+1
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* | Add flooring division operatorXiretza2020-05-282-0/+71
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* | Add flooring modulo operatorXiretza2020-05-282-3/+124
| | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* | xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-1939-24/+232
| | | | Fixes #2058.
* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-142-14/+2
| | | | instead of moving them to $__ prefix
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-142-5/+4
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* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
| | | | replacing _all_ (* abc9_box *) instantiations with their derived types
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
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* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
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* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
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* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
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* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
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* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
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* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-143-4/+4
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-148-763/+129
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
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* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
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* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
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* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
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* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
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* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
| | | | This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
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* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
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* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
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* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
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* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-145-369/+5
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* Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-142-7/+30
|\ | | | | ast: swap range regardless of range_left >= 0
| * techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-052-7/+30
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* | ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
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* | ice40: fix whitespaceEddie Hung2020-05-121-15/+14
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* | ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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