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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 15:15:20 -0700 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-04 19:45:10 +0200 |
| commit | 3db3e1e1491b426766f1da87e1da840f3fa46278 (patch) | |
| tree | 67eba12a29a5ef77dfac113e6a148d9be92a93cc /techlibs | |
| parent | 83cde2d02ba06bbd4014858983ac324bf44cb6c6 (diff) | |
| download | yosys-3db3e1e1491b426766f1da87e1da840f3fa46278.tar.gz yosys-3db3e1e1491b426766f1da87e1da840f3fa46278.tar.bz2 yosys-3db3e1e1491b426766f1da87e1da840f3fa46278.zip | |
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/intel_alm/common/abc9_map.v | 2 | ||||
| -rw-r--r-- | techlibs/intel_alm/common/abc9_model.v | 2 | ||||
| -rw-r--r-- | techlibs/intel_alm/common/abc9_unmap.v | 2 | ||||
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/intel_alm/common/abc9_map.v b/techlibs/intel_alm/common/abc9_map.v index 32ad79bdc..9d11bb240 100644 --- a/techlibs/intel_alm/common/abc9_map.v +++ b/techlibs/intel_alm/common/abc9_map.v @@ -11,7 +11,7 @@ parameter _TECHMAP_CONSTMSK_ACLR_ = 1'b0; // If the async-clear is constant, we assume it's disabled. if (_TECHMAP_CONSTMSK_ACLR_ != 1'b0) - MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q)); + $__MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q)); else wire _TECHMAP_FAIL_ = 1; diff --git a/techlibs/intel_alm/common/abc9_model.v b/techlibs/intel_alm/common/abc9_model.v index dd46147a5..8ad52e13a 100644 --- a/techlibs/intel_alm/common/abc9_model.v +++ b/techlibs/intel_alm/common/abc9_model.v @@ -18,7 +18,7 @@ // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis. (* abc9_flop, lib_whitebox *) -module MISTRAL_FF_SYNCONLY( +module $__MISTRAL_FF_SYNCONLY ( input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA, output reg Q ); diff --git a/techlibs/intel_alm/common/abc9_unmap.v b/techlibs/intel_alm/common/abc9_unmap.v index 0eda69560..4b28866a3 100644 --- a/techlibs/intel_alm/common/abc9_unmap.v +++ b/techlibs/intel_alm/common/abc9_unmap.v @@ -1,7 +1,7 @@ // After performing sequential synthesis, map the synchronous flops back to // standard MISTRAL_FF flops. -module MISTRAL_FF_SYNCONLY( +module $__MISTRAL_FF_SYNCONLY ( input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA, output reg Q ); diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 982857dd5..4bc943cb2 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -173,7 +173,7 @@ struct SynthIntelALMPass : public ScriptPass { run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/abc9_model.v", family_opt.c_str())); + run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str())); // Misc and common cells run("read_verilog -lib +/intel/common/altpll_bb.v"); |