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* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
|\ | | | | equiv_opt: new command, for verifying optimization passes
| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-0/+2
| | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
* | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
|\ \ | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass
| * | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
| |/ | | | | | | | | | | | | This is useful if you want to place FF manually ... can't merge SR in those because it might make the manual placement invalid Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
|\ \ | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys
| * | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
| |/ | | | | | | | | | | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys
* / synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
| | | | This should be combined with -relut to get sensible results.
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-052-0/+88
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* Fix typo.whitequark2018-12-051-2/+2
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* Merge pull request #713 from Diego-HR/masterClifford Wolf2018-12-055-12/+91
|\ | | | | Changes in GoWin synth commands and ALU primitive support
| * Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-035-12/+91
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* | Merge pull request #712 from mmicko/anlogic-supportClifford Wolf2018-12-057-0/+1278
|\ \ | | | | | | Initial support for Anlogic FPGA
| * | Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
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| * | Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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* | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-2/+2
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* | synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
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* | Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
| | | | | | | | | | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
* | ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
|/ | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #697 from eddiehung/xilinx_ps7Clifford Wolf2018-11-122-0/+624
|\ | | | | Add support for PS7 block for Xilinx
| * Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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* | Merge pull request #695 from daveshah1/ecp5_bbClifford Wolf2018-11-122-1/+420
|\ \ | |/ |/| ecp5: Adding some blackbox cells
| * ecp5: Add 'fake' DCU parametersDavid Shah2018-11-091-0/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Add blackboxes for ancillary DCU cellsDavid Shah2018-11-091-0/+18
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Adding some blackbox cellsDavid Shah2018-11-072-1/+391
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
|\ | | | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
| * xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| | | | | | | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* | ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | BRAM improvementsDavid Shah2018-10-121-11/+16
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* Merge pull request #645 from daveshah1/ecp5_dram_fixClifford Wolf2018-10-021-0/+1
|\ | | | | ecp5: Don't map ROMs to DRAM
| * ecp5: Don't map ROMs to DRAMDavid Shah2018-10-011-0/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-2016-54/+54
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
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