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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-02 10:00:10 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-02 10:00:10 +0200 |
| commit | 76baae4b946cdeb04026120b495c87a6146358d0 (patch) | |
| tree | 8c89ec0a22d7571530a96901f9a2f2ecf374c254 /techlibs | |
| parent | 0a7751a11bab536dbdc1534fc8c98033d4998bcb (diff) | |
| parent | fcd39e1398b950aa19c5fec157770bd7c3fa2227 (diff) | |
| download | yosys-76baae4b946cdeb04026120b495c87a6146358d0.tar.gz yosys-76baae4b946cdeb04026120b495c87a6146358d0.tar.bz2 yosys-76baae4b946cdeb04026120b495c87a6146358d0.zip | |
Merge pull request #645 from daveshah1/ecp5_dram_fix
ecp5: Don't map ROMs to DRAM
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/dram.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt index b3252fa9a..b94357429 100644 --- a/techlibs/ecp5/dram.txt +++ b/techlibs/ecp5/dram.txt @@ -13,4 +13,5 @@ endbram match $__TRELLIS_DPR16X4 make_outreg + min wports 1 endmatch |