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| | * | | Merge pull request #941 from Wren6991/sim_lib_io_clkeClifford Wolf2019-04-221-10/+19
| | |\ \ \ | | | | | | | | | | | | ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
| | | * | | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵Luke Wren2019-04-211-10/+19
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| | * | | | Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-masterClifford Wolf2019-04-2210-10/+458
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| | | * | | | GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flowDiego2019-04-1210-11/+459
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| | * | | | Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Merge pull request #916 from YosysHQ/map_cells_before_map_lutsClifford Wolf2019-04-221-10/+10
| | |\ \ \ \ | | | | | | | | | | | | | | synth_xilinx to map_cells before map_luts
| | * \ \ \ \ Merge pull request #911 from mmicko/gowin-nobramClifford Wolf2019-04-221-1/+1
| | |\ \ \ \ \ | | | |_|_|_|/ | | |/| | | | Make nobram false by default for gowin
| | | * | | | Make nobram false by default for gowinMiodrag Milanovic2019-04-021-1/+1
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| * | | | | | Tidy up, fix for -nosrlEddie Hung2019-04-212-12/+16
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| * | | | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| | * | | | | Merge branch 'master' into map_cells_before_map_lutsEddie Hung2019-04-216-59/+85
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| * | | | | | Add commentsEddie Hung2019-04-211-0/+7
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| * | | | | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
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| * | | | | | Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-204-44/+69
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| | * | | | | Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-1811-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.
| | * | | | | Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-184-44/+69
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| | * | | | | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-1011-15/+15
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| * | | | | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-052-8/+14
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| * | | | | | Move dffinit til after abcEddie Hung2019-04-053-2/+2
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| * | | | | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-054-11/+12
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| | * | | | | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
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| | * | | | | RetryEddie Hung2019-04-051-1/+1
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| | * | | | | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
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| | * | | | | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
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| * | | | | techmap inside map_cells stageEddie Hung2019-04-052-2/+1
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| * | | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| | * | | | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
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| * | | | | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
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| * | | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| | * | | | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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| * | | | Cleanup commentsEddie Hung2019-04-041-5/+4
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| * | | | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
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| * | | | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
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| * | | | Remove duplicate STARTUPE2Eddie Hung2019-04-031-1/+0
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| * | | | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
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| * | | | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
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| * | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-222-24/+31
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| * | | | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
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| * | | | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
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| * | | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-53/+20
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| * | | | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-11/+67
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| * | | | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
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| * | | | Fix spacingEddie Hung2019-03-191-1/+1
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| * | | | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
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| * | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * | | | | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-5/+1
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| * | | | | Cleanup synth_xilinxEddie Hung2019-03-152-3/+2
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| * | | | | WorkingEddie Hung2019-03-152-47/+78
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| * | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted firstEddie Hung2019-03-141-16/+32
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| * | | | | MisspellEddie Hung2019-03-141-1/+1
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