diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:01:00 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-22 09:01:00 +0200 |
| commit | cbd9b8a3f38b15874d36e5ba116536a981756411 (patch) | |
| tree | 080b5e2902cb56ce5a5a6c6c34e69d25a2819972 /techlibs | |
| parent | 19fd411e77be57eb6b7a273b8acaa25d462186ef (diff) | |
| parent | a3371e118b05eb9bd5dddb1c20758674ae50a803 (diff) | |
| download | yosys-cbd9b8a3f38b15874d36e5ba116536a981756411.tar.gz yosys-cbd9b8a3f38b15874d36e5ba116536a981756411.tar.bz2 yosys-cbd9b8a3f38b15874d36e5ba116536a981756411.zip | |
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
synth_xilinx to map_cells before map_luts
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 397c83ac6..da6c0a4b2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -113,17 +113,17 @@ struct SynthXilinxPass : public Pass log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); + log(" map_cells:\n"); + log(" techmap -map +/xilinx/cells_map.v\n"); + log(" clean\n"); + log("\n"); log(" map_luts:\n"); log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); - log("\n"); - log(" map_cells:\n"); - log(" techmap -map +/xilinx/cells_map.v\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); - log(" clean\n"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); @@ -266,20 +266,20 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -fast"); } + if (check_label(active, run_from, run_to, "map_cells")) + { + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "clean"); + } + if (check_label(active, run_from, run_to, "map_luts")) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); - } - - if (check_label(active, run_from, run_to, "map_cells")) - { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); - Pass::call(design, "clean"); } if (check_label(active, run_from, run_to, "check")) |