| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | ecp5: Add attrmvcp to copy syn_useioff to driving FF | David Shah | 2019-10-10 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | ecp5: Set syn_useioff on IO FFs to enable packing | David Shah | 2019-10-10 | 1 | -8/+8 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 5 | -33/+14 | |
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| | * | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 31 | -228/+236 | |
| | |\ \ \ | | | | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | |||||
| | | * \ \ | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 4 | -181/+9 | |
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| | | * | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 31 | -227/+235 | |
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| | * | | | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 | |
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| | * | | | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| | * | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 | |
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| | * | | | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 | |
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| | * | | | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 | |
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| | * | | | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| | * | | | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 | |
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| * | | | | FF should be initialized to 0 | Miodrag Milanovic | 2019-10-04 | 1 | -1/+3 | |
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| * | | | | Add missing latch mapping | Miodrag Milanovic | 2019-10-04 | 1 | -0/+12 | |
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| * | | | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 | |
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| * | | | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 2 | -2/+76 | |
| | | | | | | | | | | | | | Fixes #1387. | |||||
| * | | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 19 | -31/+3395 | |
| |\ \ \ | | | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | |||||
| | * | | | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 | |
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| | * | | | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 | |
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| | * | | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 | |
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| | * | | | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 | |
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| | * | | | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 | |
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| | * | | | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 3 | -38/+14 | |
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| | * | | | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 | |
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| | * | | | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 | |
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| | * | | | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 | |
| | | | | | | | | | | | | | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. | |||||
| | * | | | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 | |
| | | | | | | | | | | | | | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. | |||||
| | * | | | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 | |
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| | * | | | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 | |
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| | * | | | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 | |
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| | * | | | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 | |
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| | * | | | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 | |
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| | * | | | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
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| | * | | | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
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| | * | | | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 | |
| | | | | | | | | | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | |||||
| | * | | | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 | |
| | | | | | | | | | | | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b. | |||||
| | * | | | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98. | |||||
| | * | | | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
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| | * | | | Remove (* techmap_autopurge *) from abc_unmap.v since no effect | Eddie Hung | 2019-09-23 | 1 | -38/+38 | |
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| | * | | | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 3 | -0/+87 | |
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| | * | | | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 | |
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| | * | | | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
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| | * | | | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 2 | -3/+2 | |
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| | * | | | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 | |
| | | | | | | | | | | | | | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab. | |||||
| | * | | | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 | |
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| | * | | | Tidy up, fix undriven | Eddie Hung | 2019-09-19 | 1 | -32/+34 | |
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| | * | | | $__ABC_REG to have WIDTH parameter | Eddie Hung | 2019-09-19 | 2 | -17/+18 | |
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index : iCE40/yosys | |
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