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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 14:21:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 14:21:47 -0700 |
| commit | 90236025b7e1409027550451abe4ffc1cc63f128 (patch) | |
| tree | 2b469d460a828bde9991efa4e574879b9b6f55dc /techlibs | |
| parent | aebbfffd71ab6a85f86ef44f40b1d46a7d6a60ee (diff) | |
| download | yosys-90236025b7e1409027550451abe4ffc1cc63f128.tar.gz yosys-90236025b7e1409027550451abe4ffc1cc63f128.tar.bz2 yosys-90236025b7e1409027550451abe4ffc1cc63f128.zip | |
Missing (* mul2dsp *) for sliceB
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6dcdcf226..4cabb4453 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -198,7 +198,7 @@ module _80_mul (A, B, Y); if (i == 0)
assign partial_sum[i] = partial[i];
else
- assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
+ assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
end
\$__mul #(
@@ -212,7 +212,7 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]),
.Y(last_partial)
);
- assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
+ assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
assign Y = partial_sum[n];
end
else begin
|