Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ecp5: remove small LUT entries | Eddie Hung | 2020-02-27 | 1 | -24/+6 |
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* | Fix commented out specify statement | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
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* | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 5 | -446/+519 |
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* | ecp5: deprecate abc9_{arrival,required} and *.{lut,box} | Eddie Hung | 2020-02-27 | 7 | -86/+120 |
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* | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 1 | -176/+404 |
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* | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 7 | -426/+151 |
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* | abc9_ops: -prep_box, to be called once | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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* | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 2 | -4/+85 |
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* | Merge pull request #1709 from rqou/coolrunner2_counter | Claire Wolf | 2020-02-27 | 3 | -0/+165 |
|\ | | | | | Improve CoolRunner-II optimization by using extract_counter pass | ||||
| * | coolrunner2: Use extract_counter to optimize counters | R. Ou | 2020-02-17 | 3 | -0/+165 |
| | | | | | | | | | | This tends to make much more efficient pterm usage compared to just throwing the problem at ABC | ||||
* | | Merge pull request #1708 from rqou/coolrunner2-buf-fix | Claire Wolf | 2020-02-27 | 4 | -54/+163 |
|\ \ | | | | | | | coolrunner2: Separate and improve buffer cell insertion pass | ||||
| * | | coolrunner2: Separate and improve buffer cell insertion pass | R. Ou | 2020-02-16 | 4 | -54/+163 |
| |/ | | | | | | | | | | | | | The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between. | ||||
* / | xilinx: mark IOBUFDSE3 IOB pin as external | Piotr Binkowski | 2020-02-27 | 2 | -1/+2 |
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* | Remove executable flag from files | Miodrag Milanovic | 2020-02-15 | 5 | -0/+0 |
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* | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr | Eddie Hung | 2020-02-13 | 1 | -11/+12 |
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* | abc9: cleanup | Eddie Hung | 2020-02-10 | 1 | -40/+40 |
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* | Remove unnecessary comma | Eddie Hung | 2020-02-07 | 1 | -3/+2 |
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* | techmap: fix shiftx2mux decomposition | Eddie Hung | 2020-02-07 | 1 | -8/+6 |
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* | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 4 | -27/+22 |
| | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 | ||||
* | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 3 | -53/+152 |
| | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547 | ||||
* | Merge pull request #1685 from dh73/gowin | Eddie Hung | 2020-02-06 | 1 | -1/+1 |
|\ | | | | | Removing cells_sim from GoWin bram techmap | ||||
| * | Removing cells_sim.v from bram techmap pass | Diego H | 2020-02-06 | 1 | -1/+1 |
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* | | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 11 | -1/+370 |
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* | | xilinx: Add support for Spartan 3A DSP block RAMs. | Marcin Kościelnicki | 2020-02-07 | 3 | -1/+39 |
| | | | | | | | | Part of #1550 | ||||
* | | Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map | Eddie Hung | 2020-02-06 | 1 | -109/+43 |
|\ \ | |/ |/| | Fix/cleanup +/xilinx/arith_map.v | ||||
| * | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk | Eddie Hung | 2020-02-06 | 1 | -4/+5 |
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| * | Fix/cleanup +/xilinx/arith_map.v | Eddie Hung | 2020-02-06 | 1 | -111/+44 |
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* | | synth_*: call 'opt -fast' after 'techmap' | Eddie Hung | 2020-02-05 | 8 | -5/+9 |
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* | | shiftx2mux: fix select out of bounds | Eddie Hung | 2020-02-05 | 1 | -1/+2 |
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* | Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux | Eddie Hung | 2020-02-05 | 24 | -359/+1041 |
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| * | Merge pull request #1661 from YosysHQ/eddie/abc9_required | Eddie Hung | 2020-02-05 | 7 | -144/+375 |
| |\ | | | | | | | abc9: add support for required times | ||||
| | * | Merge branch 'eddie/abc9_refactor' into eddie/abc9_required | Eddie Hung | 2020-01-27 | 5 | -129/+99 |
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| | * \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-15 | 1 | -1/+1 |
| | |\ \ | | | | | | | | | | | | | | | | eddie/abc9_required | ||||
| | * | | | abc9_ops: -write_box is empty, output a dummy box to prevent ABC error | Eddie Hung | 2020-01-15 | 2 | -2/+0 |
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| | * | | | abc9_ops: generate flop box ids, add abc9_required to FD* cells | Eddie Hung | 2020-01-14 | 1 | -12/+45 |
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| | * | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-14 | 3 | -23/+30 |
| | |\ \ \ | | | | | | | | | | | | | | | | | | | eddie/abc9_required | ||||
| | * \ \ \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-12 | 2 | -3/+2 |
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required | ||||
| | * | | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN} | Eddie Hung | 2020-01-10 | 1 | -38/+117 |
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| | * | | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attr | Eddie Hung | 2020-01-10 | 1 | -61/+0 |
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| | * | | | | | Add abc9_ops -check, -prep_times, -write_box for required times | Eddie Hung | 2020-01-10 | 1 | -0/+5 |
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| | * | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-08 | 6 | -1676/+520 |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required | ||||
| | * \ \ \ \ \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-06 | 39 | -656/+1189 |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | xaig_arrival_required | ||||
| | | * \ \ \ \ \ | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor | Eddie Hung | 2020-01-02 | 12 | -756/+722 |
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| | | * \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2020-01-02 | 27 | -91/+118 |
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| | | * \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor | Eddie Hung | 2019-12-30 | 6 | -121/+673 |
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| | * | | | | | | | | | | Consistency | Eddie Hung | 2019-12-27 | 1 | -1/+1 |
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| | * | | | | | | | | | | Update some abc9_arrival times, add abc9_required times | Eddie Hung | 2019-12-27 | 3 | -24/+220 |
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| * | | | | | | | | | | | Add opt_lut_ins pass. (#1673) | Marcelina Kościelnicka | 2020-02-03 | 3 | -0/+3 |
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| * | | | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read ports | Marcin Kościelnicki | 2020-02-02 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files). | ||||
| * | | | | | | | | | | | Merge pull request #1659 from YosysHQ/clifford/experimental | Claire Wolf | 2020-01-29 | 1 | -1/+1 |
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x" |