xilinx: use specify blocks in place of abc9_{arrival,required}

1 files changed, 404 insertions, 176 deletions

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1318389f0..f9d837e4c 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -477,18 +477,14 @@ endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDRE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
   (* invertible_pin = "IS_R_INVERTED" *)
-  (* abc9_required=404 *)
   input R
 );
   parameter [0:0] INIT = 1'b0;
@@ -496,44 +492,58 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
+  generate
+  case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //$setup(D , posedge C, -46); // Negative times not currently supported
+      $setup(CE, posedge C, 109);
+      $setup(R , posedge C, 404);
+    endspecify
+  else
+    specify
+      if (CE) (negedge C => (Q : D)) = 303;
+      //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+      $setup(CE, negedge C, 109);
+      $setup(R , negedge C, 404);
+    endspecify
+  endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDRE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
-  (* abc9_required=404 *)
   input R
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    $setup(CE, negedge C, 109);
+    $setup(R , negedge C, 404);
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDSE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
   (* invertible_pin = "IS_S_INVERTED" *)
-  (* abc9_required=404 *)
   input S
 );
   parameter [0:0] INIT = 1'b1;
@@ -541,28 +551,46 @@ module FDSE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
+  generate
+  case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //if (CE) $setup(D , posedge C, -46); // Negative times not currently supported
+      $setup(CE, posedge C, 109);
+      $setup(S , posedge C, 404);
+    endspecify
+  else
+    specify
+        if (CE) (negedge C => (Q : D)) = 303;
+        //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+        $setup(CE, negedge C, 109);
+        $setup(S , negedge C, 404);
+    endspecify
+  endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDSE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
-  (* abc9_required=404 *)
   input S
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    $setup(CE, negedge C, 109);
+    $setup(S , negedge C, 404);
+  endspecify
 endmodule
 
 module FDRSE (
@@ -571,7 +599,6 @@ module FDRSE (
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
   (* invertible_pin = "IS_CE_INVERTED" *)
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
   input D,
@@ -603,18 +630,14 @@ endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDCE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_CLR_INVERTED" *)
-  (* abc9_required=764 *)
   input CLR,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D
 );
   parameter [0:0] INIT = 1'b0;
@@ -622,46 +645,60 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
+  generate
+  case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
+      $setup(CE , posedge C, 109);
+      $setup(CLR, posedge C, 764);
+    endspecify
+  else
+    specify
+        if (CE) (negedge C => (Q : D)) = 303;
+        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+        $setup(CE , negedge C, 109);
+        $setup(CLR, negedge C, 764);
+    endspecify
+ endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDCE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  (* abc9_required=764 *)
   input CLR,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    $setup(CE , negedge C, 109);
+    $setup(CLR, negedge C, 764);
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDPE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
   (* invertible_pin = "IS_PRE_INVERTED" *)
-  (* abc9_required=764 *)
   input PRE
 );
   parameter [0:0] INIT = 1'b1;
@@ -674,25 +711,42 @@ module FDPE (
     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
+      $setup(CE , posedge C, 109);
+      $setup(PRE, posedge C, 764);
+    endspecify
+  else
+    specify
+        if (CE) (negedge C => (Q : D)) = 303;
+        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+        $setup(CE , negedge C, 109);
+        $setup(PRE, negedge C, 764);
+    endspecify
+  endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDPE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
-  (* abc9_required=764 *)
   input PRE
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    $setup(CE , negedge C, 109);
+    $setup(PRE, negedge C, 764);
+  endspecify
 endmodule
 
 module FDCPE (
@@ -1303,33 +1357,13 @@ module RAM16X1D_1 (
 endmodule
 
 module RAM32X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-  (* abc9_required=245 *)
-  input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
-  (* abc9_required=208 *)
-  input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-  (* abc9_required=147 *)
-  input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-  (* abc9_required=68 *)
-  input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-  (* abc9_required=66 *)
-  input  A4,
+  input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
   parameter INIT = 32'h0;
@@ -1341,35 +1375,61 @@ module RAM32X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (posedge WCLK => (SPO : D)) = 1153;
+        if (WE) (posedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , posedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+        $setup(A0, posedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+        $setup(A1, posedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+        $setup(A2, posedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+        $setup(A3, posedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+        $setup(A4, posedge WCLK, 66);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (negedge WCLK => (SPO : D)) = 1153;
+        if (WE) (negedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , negedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+        $setup(A0, negedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+        $setup(A1, negedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+        $setup(A2, negedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+        $setup(A3, negedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+        $setup(A4, negedge WCLK, 66);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM32X1D_1 (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-  (* abc9_required=245 *)
   input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
-  (* abc9_required=208 *)
   input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-  (* abc9_required=147 *)
   input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-  (* abc9_required=68 *)
   input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-  (* abc9_required=66 *)
   input  A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -1382,39 +1442,35 @@ module RAM32X1D_1 (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => (SPO : D)) = 1153;
+    if (WE) (negedge WCLK => (DPO : D)) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , negedge WCLK, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, negedge WCLK, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+    $setup(A0, negedge WCLK, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+    $setup(A1, negedge WCLK, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+    $setup(A2, negedge WCLK, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+    $setup(A3, negedge WCLK, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+    $setup(A4, negedge WCLK, 66);
+  endspecify
 endmodule
 
 module RAM64X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-  (* abc9_required=362 *)
-  input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-  (* abc9_required=245 *)
-  input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-  (* abc9_required=208 *)
-  input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-  (* abc9_required=147 *)
-  input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-  (* abc9_required=68 *)
-  input  A4,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-  (* abc9_required=66 *)
-  input  A5,
+  input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
   parameter INIT = 64'h0;
@@ -1426,39 +1482,62 @@ module RAM64X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (posedge WCLK => (SPO : D)) = 1153;
+        if (WE) (posedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , posedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+        $setup(A0, posedge WCLK, 362);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+        $setup(A1, posedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+        $setup(A2, posedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+        $setup(A3, posedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+        $setup(A4, posedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+        $setup(A5, posedge WCLK, 66);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (negedge WCLK => (SPO : D)) = 1153;
+        if (WE) (negedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , negedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+        $setup(A0, negedge WCLK, 362);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+        $setup(A1, negedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+        $setup(A2, negedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+        $setup(A3, negedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+        $setup(A4, negedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+        $setup(A5, negedge WCLK, 66);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM64X1D_1 (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-  (* abc9_required=362 *)
-  input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-  (* abc9_required=245 *)
-  input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-  (* abc9_required=208 *)
-  input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-  (* abc9_required=147 *)
-  input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-  (* abc9_required=68 *)
-  input  A4,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-  (* abc9_required=66 *)
-  input  A5,
+  input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
   parameter INIT = 64'h0;
@@ -1470,21 +1549,35 @@ module RAM64X1D_1 (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => (SPO : D)) = 1153;
+    if (WE) (negedge WCLK => (DPO : D)) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , negedge WCLK, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, negedge WCLK, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+    $setup(A0, negedge WCLK, 362);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+    $setup(A1, negedge WCLK, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+    $setup(A2, negedge WCLK, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+    $setup(A3, negedge WCLK, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+    $setup(A4, negedge WCLK, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+    $setup(A5, negedge WCLK, 66);
+  endspecify
 endmodule
 
 module RAM128X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  //   plus 208ps to cross MUXF7
-  (* abc9_arrival=1359 *)
   output       DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input        D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input        WE,
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
   (* abc9_required="616 362 245 208 147 68 66" *)
@@ -1498,6 +1591,46 @@ module RAM128X1D (
   assign DPO = mem[DPRA];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        //   plus 208ps to cross MUXF7
+        if (WE) (posedge WCLK => (SPO : D)) = 1359;
+        if (WE) (posedge WCLK => (DPO : D)) = 1359;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , posedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
+        $setup(A[0], posedge WCLK, 616);
+        $setup(A[1], posedge WCLK, 362);
+        $setup(A[2], posedge WCLK, 245);
+        $setup(A[3], posedge WCLK, 208);
+        $setup(A[4], posedge WCLK, 147);
+        $setup(A[5], posedge WCLK, 68);
+        $setup(A[6], posedge WCLK, 66);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        //   plus 208ps to cross MUXF7
+        if (WE) (negedge WCLK => (SPO : D)) = 1359;
+        if (WE) (negedge WCLK => (DPO : D)) = 1359;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , negedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
+        $setup(A[0], negedge WCLK, 616);
+        $setup(A[1], negedge WCLK, 362);
+        $setup(A[2], negedge WCLK, 245);
+        $setup(A[3], negedge WCLK, 208);
+        $setup(A[4], negedge WCLK, 147);
+        $setup(A[5], negedge WCLK, 68);
+        $setup(A[6], negedge WCLK, 66);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM256X1D (
@@ -1521,43 +1654,19 @@ endmodule
 // Multi port.
 
 module RAM32M (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
-  (* abc9_arrival="1153 1188" *)
   output [1:0] DOA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
-  (* abc9_arrival="1161 1187" *)
   output [1:0] DOB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
-  (* abc9_arrival="1158 1180" *)
   output [1:0] DOC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
-  (* abc9_arrival="1163 1190" *)
   output [1:0] DOD,
   input  [4:0] ADDRA, ADDRB, ADDRC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792-L802
-  (* abc9_required="245 208 147 68 66" *)
   input  [4:0] ADDRD,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-  (* abc9_required="453 384" *)
   input  [1:0] DIA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-  (* abc9_required="461 354" *)
   input  [1:0] DIB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-  (* abc9_required="457 375" *)
   input  [1:0] DIC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-  (* abc9_required="310 334" *)
   input  [1:0] DID,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input        WE
 );
   parameter [63:0] INIT_A = 64'h0000000000000000;
@@ -1581,6 +1690,87 @@ module RAM32M (
       mem_c[2*ADDRD+:2] <= DIC;
       mem_d[2*ADDRD+:2] <= DID;
     end
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+        if (WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
+        if (WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
+        if (WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
+        if (WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(ADDRD[0], posedge WCLK, 245);
+        $setup(ADDRD[1], posedge WCLK, 208);
+        $setup(ADDRD[2], posedge WCLK, 147);
+        $setup(ADDRD[3], posedge WCLK, 68);
+        $setup(ADDRD[4], posedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA[0], posedge WCLK, 453);
+        $setup(DIA[1], posedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB[0], posedge WCLK, 461);
+        $setup(DIB[1], posedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC[0], posedge WCLK, 457);
+        $setup(DIC[1], posedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID[0], posedge WCLK, 310);
+        $setup(DID[1], posedge WCLK, 334);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+        if (WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
+        if (WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
+        if (WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
+        if (WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(ADDRD[0], negedge WCLK, 245);
+        $setup(ADDRD[1], negedge WCLK, 208);
+        $setup(ADDRD[2], negedge WCLK, 147);
+        $setup(ADDRD[3], negedge WCLK, 68);
+        $setup(ADDRD[4], negedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA[0], negedge WCLK, 453);
+        $setup(DIA[1], negedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB[0], negedge WCLK, 461);
+        $setup(DIB[1], negedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC[0], negedge WCLK, 457);
+        $setup(DIC[1], negedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID[0], negedge WCLK, 310);
+        $setup(DID[1], negedge WCLK, 334);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+      endspecify
+  endgenerate
+
 endmodule
 
 module RAM32M16 (
@@ -1653,39 +1843,19 @@ module RAM32M16 (
 endmodule
 
 module RAM64M (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-  (* abc9_arrival=1153 *)
   output       DOA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc9_arrival=1161 *)
   output       DOB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-  (* abc9_arrival=1158 *)
   output       DOC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-  (* abc9_arrival=1163 *)
   output       DOD,
   input  [5:0] ADDRA, ADDRB, ADDRC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
-  (* abc9_required="362 245 208 147 68 66" *)
   input  [5:0] ADDRD,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-  (* abc9_required=384 *)
   input        DIA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-  (* abc9_required=354 *)
   input        DIB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-  (* abc9_required=375 *)
   input        DIC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-  (* abc9_required=310 *)
   input        DID,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input        WE
 );
   parameter [63:0] INIT_A = 64'h0000000000000000;
@@ -1709,6 +1879,64 @@ module RAM64M (
       mem_c[ADDRD] <= DIC;
       mem_d[ADDRD] <= DID;
     end
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (posedge WCLK => (DOA : DIA)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (posedge WCLK => (DOB : DIB)) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (posedge WCLK => (DOC : DIC)) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (posedge WCLK => (DOD : DID)) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
+        $setup(ADDRD[0], posedge WCLK, 362);
+        $setup(ADDRD[1], posedge WCLK, 245);
+        $setup(ADDRD[2], posedge WCLK, 208);
+        $setup(ADDRD[3], posedge WCLK, 147);
+        $setup(ADDRD[4], posedge WCLK, 68);
+        $setup(ADDRD[5], posedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA, posedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB, posedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC, posedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID, posedge WCLK, 310);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (negedge WCLK => (DOA : DIA)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (negedge WCLK => (DOB : DIB)) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (negedge WCLK => (DOC : DIC)) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (negedge WCLK => (DOD : DID)) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
+        $setup(ADDRD[0], negedge WCLK, 362);
+        $setup(ADDRD[1], negedge WCLK, 245);
+        $setup(ADDRD[2], negedge WCLK, 208);
+        $setup(ADDRD[3], negedge WCLK, 147);
+        $setup(ADDRD[4], negedge WCLK, 68);
+        $setup(ADDRD[5], negedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA, negedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB, negedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC, negedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID, negedge WCLK, 310);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM64M8 (