| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Added GP_COUNT8/GP_COUNT14 cells | Andrew Zonenberg | 2016-03-26 | 1 | -0/+22 | |
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| * | Changed GP_LFOSC parameter configuration | Andrew Zonenberg | 2016-03-26 | 1 | -1/+3 | |
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| * | Added GP_LFOSC cell | Andrew Zonenberg | 2016-03-26 | 1 | -0/+17 | |
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| * | Renamed GP4_V* cells to GP_V* for consistency | Andrew Zonenberg | 2016-03-26 | 1 | -2/+3 | |
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| * | Added GP_DFFS, GP_DFFR, and GP_DFFSR | Clifford Wolf | 2016-03-23 | 4 | -21/+76 | |
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| * | Added GP_DFF INIT parameter | Clifford Wolf | 2016-03-23 | 2 | -0/+4 | |
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| * | Improvements in synth_greenpak4, added -part option | Clifford Wolf | 2016-03-21 | 1 | -30/+25 | |
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| * | Added black box modules for all the 7-series design elements (as listed in ↵ | Clifford Wolf | 2016-03-19 | 4 | -0/+3441 | |
| | | | | | ug953) | |||||
| * | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 | 1 | -0/+2 | |
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| * | Work around DDR dout sim glitches in ice40 SB_IO sim model | Clifford Wolf | 2016-02-07 | 1 | -1/+7 | |
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| * | Added dffsr2dff | Clifford Wolf | 2016-02-02 | 1 | -0/+2 | |
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| * | Progress in cell library documentation | Clifford Wolf | 2016-02-01 | 1 | -0/+238 | |
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| * | Added "abc -luts" option, Improved Xilinx logic mapping | Clifford Wolf | 2016-02-01 | 1 | -2/+2 | |
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| * | Re-run ice40_opt in "synth_ice40 -abc2" | Clifford Wolf | 2015-12-22 | 1 | -1/+4 | |
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| * | Improvements in ice40_opt | Clifford Wolf | 2015-12-22 | 1 | -5/+16 | |
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| * | Bugfix in ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -2/+2 | |
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| * | Improved ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -1/+22 | |
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| * | Run opt_const before check in default scripts | Clifford Wolf | 2015-12-22 | 2 | -0/+4 | |
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| * | Added "synth_ice40 -abc2" | Clifford Wolf | 2015-12-08 | 1 | -0/+11 | |
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| * | Merge pull request #108 from cseed/master | Clifford Wolf | 2015-12-07 | 1 | -1/+3 | |
| |\ | | | | | Added LO to ICESTORM_LC for LUT cascade route. | |||||
| | * | Added LO to ICESTORM_LC for LUT cascade route. | Cotton Seed | 2015-12-06 | 1 | -1/+3 | |
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| * | | Added ice40_ffinit pass | Clifford Wolf | 2015-11-26 | 3 | -0/+145 | |
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| * | | Fixed WE/RE usage in iCE40 BRAM mapping | Clifford Wolf | 2015-11-24 | 1 | -8/+8 | |
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| * | | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling | Clifford Wolf | 2015-11-06 | 1 | -2/+2 | |
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| * | | Bugfix in Xilinx LUT mapping | Clifford Wolf | 2015-10-30 | 1 | -1/+1 | |
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| * | | Progress on cell help messages | Clifford Wolf | 2015-10-20 | 1 | -18/+114 | |
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| * | | Progress on cell help messages | Clifford Wolf | 2015-10-17 | 2 | -53/+106 | |
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| * | | Added "prep" command | Clifford Wolf | 2015-10-14 | 2 | -0/+157 | |
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| * | | Added more cell descriptions | Clifford Wolf | 2015-10-14 | 1 | -0/+85 | |
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| * | | Added first help messages for cell types | Clifford Wolf | 2015-10-14 | 4 | -0/+292 | |
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| * | | Added examples/ top-level directory | Clifford Wolf | 2015-10-13 | 14 | -279/+0 | |
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| * | | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 6 | -29/+36 | |
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| * | | Added nlutmap | Clifford Wolf | 2015-09-18 | 1 | -2/+2 | |
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| * | | Renamed GreenPAK4 cells, improved GP4 DFF mapping | Clifford Wolf | 2015-09-18 | 5 | -9/+50 | |
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| * | | Fixed copy&paste typo in synth_greenpak4 | Clifford Wolf | 2015-09-16 | 1 | -3/+3 | |
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| * | | Added GreenPAK4 skeleton | Clifford Wolf | 2015-09-16 | 4 | -0/+297 | |
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| * | | Fixed ice40 handling of negclk RAM40 | Clifford Wolf | 2015-09-10 | 2 | -12/+12 | |
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| * | | Switched to Python 3 | Clifford Wolf | 2015-08-22 | 4 | -10/+4 | |
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| * | Another bugfix for ice40 and xilinx brams_init make rules | Clifford Wolf | 2015-08-16 | 4 | -9/+9 | |
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| * | Fixed Makefile rules for generated share files | Clifford Wolf | 2015-08-16 | 2 | -2/+13 | |
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| * | Added $tribuf and $_TBUF_ sim models | Clifford Wolf | 2015-08-16 | 2 | -0/+20 | |
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| * | Added tribuf command | Clifford Wolf | 2015-08-16 | 1 | -0/+2 | |
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| * | Added $tribuf and $_TBUF_ cell types | Clifford Wolf | 2015-08-16 | 1 | -1/+1 | |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 3 | -4/+4 | |
| | | | | | Smaller this time | |||||
| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 4 | -22/+3 | |
| | | | | | This is based on work done by Larry Doolittle | |||||
| * | Improved handling of "keep" attributes in hierarchical designs in opt_clean | Clifford Wolf | 2015-08-12 | 1 | -2/+1 | |
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| * | Added iCE40 WARMBOOT cell | Marcus Comstedt | 2015-08-06 | 1 | -0/+10 | |
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| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+2 | |
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| * | Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) | Clifford Wolf | 2015-07-27 | 1 | -1/+0 | |
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| * | iCE40 DFF sim models: init Q regs to 0 | Clifford Wolf | 2015-07-20 | 1 | -20/+43 | |
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index : iCE40/yosys | |
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