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* Added simplemap $lut supportClifford Wolf2015-04-271-8/+2
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* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-273-2/+134
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* Initialization support for all iCE40 bram modesClifford Wolf2015-04-268-28/+65
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* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-255-54/+261
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* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-251-59/+83
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* More iCE40 bram improvementsClifford Wolf2015-04-254-51/+69
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* iCE40 bram progressClifford Wolf2015-04-242-16/+35
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* iCE40 bram tests and fixesClifford Wolf2015-04-246-16/+181
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* Added ice40 bram supportClifford Wolf2015-04-244-1/+192
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* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-191-13/+289
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* added sync reset to ice40 test_ffs.shClifford Wolf2015-04-183-6/+20
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* Added ice40 test_arithClifford Wolf2015-04-182-0/+13
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* Added ice40 SB_CARRY supportClifford Wolf2015-04-183-2/+81
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* Added mapping of synchronous set/reset to iCE40 flowClifford Wolf2015-04-173-4/+130
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* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-161-2/+2
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* Fixed "dff2dffe -direct-match"Clifford Wolf2015-04-161-0/+2
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* Added simple ice40 dff testsClifford Wolf2015-04-163-0/+49
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* improved ice40 dff cell mappingClifford Wolf2015-04-163-7/+46
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* use "hierarchy -auto-top" in synth_ice40Clifford Wolf2015-04-141-3/+3
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* more cells in ice40 cell libraryClifford Wolf2015-04-141-8/+289
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* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
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* Added memory_bram "make_outreg" featureClifford Wolf2015-04-091-0/+2
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* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-093-13/+67
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* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
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* Added support for initialized xilinx bramsClifford Wolf2015-04-0610-91/+314
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* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
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* Added Xilinx bram black-box modulesClifford Wolf2015-04-063-0/+322
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* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-051-6/+6
| | | | | | this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-051-0/+29
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* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-5/+6
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* Fixes in cmos_cells.vClifford Wolf2015-03-251-3/+12
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* Added very first version of "synth_ice40"Clifford Wolf2015-03-054-0/+211
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* Added $assume cell typeClifford Wolf2015-02-261-1/+18
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* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-152-0/+4
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* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-152-7/+24
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* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-151-2/+2
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* Added $meminit support to "memory" commandClifford Wolf2015-02-141-3/+15
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* Added $meminit cell typeClifford Wolf2015-02-141-0/+22
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* Added "check" commandClifford Wolf2015-02-131-0/+4
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* Some test related fixesClifford Wolf2015-02-121-4/+4
| | | | (incl. removal of three bad test cases)
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
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* no support for 6-series xilinx devicesClifford Wolf2015-02-011-1/+1
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* Removed old XST-based xilinx examplesClifford Wolf2015-02-0111-208/+0
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* Added Xilinx example for Basys3 boardClifford Wolf2015-02-019-1/+84
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* Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-011-4/+18
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* Added "make mklibyosys", some minor API changesClifford Wolf2015-02-011-1/+9
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* Added "fsm -encfile"Clifford Wolf2015-01-301-2/+9
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* Fixed xilinx FDSE sim modelClifford Wolf2015-01-241-2/+2
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* Added $equiv cell typeClifford Wolf2015-01-191-1/+23
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* Various cleanups in xilinx techlibClifford Wolf2015-01-187-9/+110
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