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| | | * | | | techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
| | | | |/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
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| * | | | | Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-126-150/+32
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* | | | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
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* | | | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
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* | | | | review fixesMarcin Kościelnicki2019-08-131-18/+27
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* | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
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* | | | Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-105-20/+14
|\ \ \ \ | | | | | | | | | | Cleanup a few barnacles across codebase
| * | | | substr() -> compare()Eddie Hung2019-08-071-3/+3
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| * | | | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
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| * | | | Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-117/+252
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| * | | | | stoi -> atoiEddie Hung2019-08-073-3/+3
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| * | | | | Fix spacingEddie Hung2019-08-061-3/+3
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| * | | | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
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| * | | | | Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
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* | | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
|\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | Add a few comments to document $alu and $lcu
| * | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
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| * | | | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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| * | | | | Add more commentsEddie Hung2019-08-091-4/+18
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| * | | | | Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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* | | | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-2/+0
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* | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-10/+17
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* | | | | Add testEddie Hung2019-08-071-1/+10
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* | | | | Remove ice40_unlutEddie Hung2019-08-072-107/+0
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* | | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* | | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
|\ \ \ \ | | | | | | | | | | ecp5: Make cells_sim.v consistent with nextpnr
| * | | | ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| |/ / / | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
|\ \ \ \ | |/ / / |/| | | anlogic : Fix alu mapping
| * | | anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
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* / / Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
|\ \ | | | | | | Fix formatting for msys2 mingw build
| * | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6
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* | | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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* | Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| * | intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| |/ | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
* | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
|\ \ | | | | | | intel: Make -noiopads the default
| * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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* | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
|\ \ \ | |/ / |/| | xilinx: Fix missing cell name underscore in cells_map.v
| * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
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* | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
|\ \ | | | | | | Assorted synth_intel cleanups from @bwidawsk
| * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
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| * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
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| * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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