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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 08:45:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 08:45:35 -0700 |
| commit | f7753720feaf466a089f4b96fca27ed4130b5be8 (patch) | |
| tree | 8f773ccb1dc6c2961f9be9e1592516a4b328740d /techlibs | |
| parent | 9cb0456b6f9fa86240a747bab9780a28001b1a02 (diff) | |
| download | yosys-f7753720feaf466a089f4b96fca27ed4130b5be8.tar.gz yosys-f7753720feaf466a089f4b96fca27ed4130b5be8.tar.bz2 yosys-f7753720feaf466a089f4b96fca27ed4130b5be8.zip | |
Don't copy ref if exists already
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/tests/test_dsp_model.sh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh index 1bc0cc688..2d42c23ad 100644 --- a/techlibs/ice40/tests/test_dsp_model.sh +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -1,7 +1,9 @@ #!/bin/bash set -ex sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v -cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +if [ ! -f "test_dsp_model_ref.v" ]; then + cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +fi for tb in testbench \ testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ testbench_seq_16x16_A testbench_seq_16x16_B |