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| * | | | | | | | | | | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| |/ / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | Trim Y_WIDTHEddie Hung2019-08-011-5/+3
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| * | | | | | | | | | | Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
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| * | | | | | | | | | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
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| * | | | | | | | | | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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| * | | | | | | | | | | Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-016-18/+24
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| * | | | | | | | | | | | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
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| * | | | | | | | | | | | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
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| * | | | | | | | | | | | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
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| * | | | | | | | | | | | Fix spacingEddie Hung2019-07-261-3/+3
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| * | | | | | | | | | | | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
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| * | | | | | | | | | | | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
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| * | | | | | | | | | | | Remove debugEddie Hung2019-07-221-1/+0
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| * | | | | | | | | | | | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
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| * | | | | | | | | | | | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
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| * | | | | | | | | | | | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
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| * | | | | | | | | | | | Indirection via $__soft_mulEddie Hung2019-07-192-9/+10
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| * | | | | | | | | | | | Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
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| * | | | | | | | | | | | Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
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| * | | | | | | | | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
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| * | | | | | | | | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
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| * | | | | | | | | | | | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| | * | | | | | | | | | | | Fix typo in BEddie Hung2019-07-191-1/+1
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| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1815-84/+164
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| * | \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * | | | | | | | | | | | | | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
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| * | | | | | | | | | | | | | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
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| * | | | | | | | | | | | | | | Add paramsEddie Hung2019-07-181-0/+6
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | | | | | | | | | | | | | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1814-51/+146
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| * | | | | | | | | | | | | | | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
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| * | | | | | | | | | | | | | | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
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| * | | | | | | | | | | | | | | Make consistentEddie Hung2019-07-181-1/+2
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| * | | | | | | | | | | | | | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
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| * | | | | | | | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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| * | | | | | | | | | | | | | | Working for unsignedEddie Hung2019-07-181-52/+28
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| * | | | | | | | | | | | | | | CleanupEddie Hung2019-07-181-70/+58
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| * | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| | * | | | | | | | | | | | | | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
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| * | | | | | | | | | | | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
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| * | | | | | | | | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
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