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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 14:33:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 14:33:16 -0700 |
| commit | 105aaeaf598a04020fa5030c947f623f0daa38da (patch) | |
| tree | cecb8b66e96e93b5ed5ceb22f719826c74a7bf7c /techlibs | |
| parent | 65de9aaaa9d744686e235ff8701cd997cd2dc891 (diff) | |
| download | yosys-105aaeaf598a04020fa5030c947f623f0daa38da.tar.gz yosys-105aaeaf598a04020fa5030c947f623f0daa38da.tar.bz2 yosys-105aaeaf598a04020fa5030c947f623f0daa38da.zip | |
Trim Y_WIDTH
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6cd5128a6..8e37201e2 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -56,20 +56,18 @@ module \$mul (A, B, Y); wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED from here
`ifdef DSP_SIGNEDONLY
- else if (!A_SIGNED) begin
- wire [1:0] _;
+ else if (!A_SIGNED)
\$mul #(
.A_SIGNED(1),
.B_SIGNED(1),
.A_WIDTH(A_WIDTH + 1),
.B_WIDTH(B_WIDTH + 1),
- .Y_WIDTH(Y_WIDTH + 2)
+ .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A({1'b0, A}),
.B({1'b0, B}),
- .Y({_, Y})
+ .Y(Y)
);
- end
`endif
else if (A_WIDTH < B_WIDTH)
\$mul #(
|