| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | | | | | | | | | | | | | Add unconditional match blocks for force RAM | Eddie Hung | 2019-12-16 | 1 | -4/+36 | |
| | | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | Update xc7/xcu bram rules | Eddie Hung | 2019-12-16 | 1 | -8/+4 | |
| | | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | Removing fixed attribute value to !ramstyle rules | Diego H | 2019-12-15 | 1 | -4/+4 | |
| | | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -18/+12 | |
| | | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+19 | |
| | | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | Merge pull request #1533 from dh73/bram_xilinx | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1 | |||||
| | * | | | | | | | | | | | | | | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. | Diego H | 2019-12-12 | 1 | -5/+5 | |
| | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | Merge https://github.com/YosysHQ/yosys into bram_xilinx | Diego H | 2019-12-12 | 20 | -775/+1170 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | ||||||
| | * | | | | | | | | | | | | | | | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 | |
| | | |_|_|_|_|_|_|_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
| | |/ / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | Fix bitwidth mismatch; suppresses iverilog warning | Eddie Hung | 2019-12-11 | 1 | -4/+4 | |
| | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | Merge pull request #1564 from ZirconiumX/intel_housekeeping | David Shah | 2019-12-11 | 8 | -6/+6 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel housekeeping | |||||
| | * | | | | | | | | | | | | | | | synth_intel: a10gx -> arria10gx | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
| | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | synth_intel: cyclone10 -> cyclone10lp | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
| | | |/ / / / / / / / / / / / / | |/| | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 4 | -20/+22 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER | |||||
| | * | | | | | | | | | | | | | | ice40_opt to restore attributes/name when unwrapping | Eddie Hung | 2019-12-09 | 1 | -0/+15 | |
| | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 2 | -19/+1 | |
| | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve | Eddie Hung | 2019-12-03 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | name and attr | |||||
| | * | | | | | | | | | | | | | | ice40_opt to ignore (* keep *) -ed cells | Eddie Hung | 2019-12-03 | 1 | -0/+5 | |
| | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 2 | -9/+16 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1225. | |||||
| * | | | | | | | | | | | | | | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 3 | -624/+831 | |
| |/ / / / / / / / / / / / / / | ||||||
| * | | | | | | | | | | | | | | Merge pull request #1524 from pepijndevos/gowindffinit | Clifford Wolf | 2019-12-03 | 2 | -112/+270 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gowin: add and test DFF init values | |||||
| | * | | | | | | | | | | | | | | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 1 | -154/+154 | |
| | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 2 | -41/+199 | |
| | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
| | |/ / / / / / / / / / / / / |/| | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
| | |_|_|_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -1/+5 | |
| | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 1 | -2/+6 | |
| |/ / / / / / / / / / / / | ||||||
| * | | | | | | | | | | / | coolrunner2: remove spurious log_pop() call, fixes #1463 | Martin Pietryka | 2019-11-23 | 1 | -2/+0 | |
| | |_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at> | |||||
| * | | | | | | | | | | | gowin: Add missing .gitignore entries | Marcin Kościelnicki | 2019-11-22 | 1 | -0/+2 | |
| | |_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | ||||||
| * | | | | | | | | | | Merge pull request #1449 from pepijndevos/gowin | Clifford Wolf | 2019-11-19 | 8 | -43/+547 | |
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Improvements for gowin support | |||||
| | * | | | | | | | | | | Remove dff init altogether | Pepijn de Vos | 2019-11-19 | 2 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware does not actually support it. In reality it is always initialised to its reset value. | |||||
| | * | | | | | | | | | | add help for nowidelut and abc9 options | Pepijn de Vos | 2019-11-18 | 1 | -1/+7 | |
| | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-16 | 4 | -15/+439 | |
| | |\ \ \ \ \ \ \ \ \ \ | ||||||
| | * | | | | | | | | | | | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 1 | -4/+4 | |
| | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-11 | 22 | -22988/+30572 | |
| | |\ \ \ \ \ \ \ \ \ \ \ | ||||||
| | * | | | | | | | | | | | | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -12/+12 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | add IOBUF | Pepijn de Vos | 2019-10-28 | 2 | -1/+10 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 2 | -2/+8 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | More formatting | Pepijn de Vos | 2019-10-28 | 1 | -55/+49 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | really really fix formatting maybe | Pepijn de Vos | 2019-10-28 | 1 | -41/+41 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | undo formatting fuckup | Pepijn de Vos | 2019-10-28 | 1 | -25/+25 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | add wide luts | Pepijn de Vos | 2019-10-28 | 3 | -36/+119 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | add 32-bit BRAM and byte-enables | Pepijn de Vos | 2019-10-28 | 2 | -4/+25 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -11/+11 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | add a few more missing dff | Pepijn de Vos | 2019-10-21 | 1 | -7/+16 | |
| | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | add negedge DFF | Pepijn de Vos | 2019-10-21 | 2 | -15/+139 | |
| | | | | | | | | | | | | | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |