| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 |
| | | |||||
| * | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | | |||||
| * | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 |
| | | |||||
| * | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
| | | |||||
| * | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 |
| | | |||||
| * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 3 | -38/+14 |
| | | |||||
| * | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 |
| | | |||||
| * | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 |
| | | |||||
| * | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 |
| | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. | ||||
| * | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. | ||||
| * | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
| | | |||||
| * | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 |
| | | |||||
| * | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | |||||
| * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 |
| | | |||||
| * | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
| | | |||||
| * | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
| | | |||||
| * | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
| | | |||||
| * | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 |
| | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | ||||
| * | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
| | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b. | ||||
| * | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
| | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98. | ||||
| * | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
| | | |||||
| * | Remove (* techmap_autopurge *) from abc_unmap.v since no effect | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
| | | |||||
| * | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 3 | -0/+87 |
| | | |||||
| * | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
| | | |||||
| * | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
| | | |||||
| * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 2 | -3/+2 |
| | | |||||
| * | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 |
| | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab. | ||||
| * | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 |
| | | |||||
| * | Tidy up, fix undriven | Eddie Hung | 2019-09-19 | 1 | -32/+34 |
| | | |||||
| * | $__ABC_REG to have WIDTH parameter | Eddie Hung | 2019-09-19 | 2 | -17/+18 |
| | | |||||
| * | Fix DSP48E1 timing by breaking P path if MREG or PREG | Eddie Hung | 2019-09-19 | 4 | -349/+363 |
| | | |||||
| * | Revert "Different approach to timing" | Eddie Hung | 2019-09-19 | 4 | -195/+405 |
| | | | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044. | ||||
| * | Different approach to timing | Eddie Hung | 2019-09-19 | 4 | -405/+195 |
| | | |||||
| * | Suppress $anyseq warnings | Eddie Hung | 2019-09-19 | 1 | -15/+32 |
| | | |||||
| * | Use (* techmap_autopurge *) to suppress techmap warnings | Eddie Hung | 2019-09-19 | 2 | -94/+99 |
| | | |||||
| * | D is 25 bits not 24 bits wide | Eddie Hung | 2019-09-19 | 1 | -1/+1 |
| | | |||||
| * | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 8 | -90/+502 |
| |\ | |||||
| | * | Use extractinv for synth_xilinx -ise | Marcin Kościelnicki | 2019-09-19 | 8 | -90/+502 |
| | | | |||||
| * | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 |
| | | | |||||
| * | | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 | Eddie Hung | 2019-09-19 | 1 | -1/+3 |
| | | | |||||
| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 9 | -948/+19414 |
| |\| | |||||
| | * | Merge pull request #1379 from mmicko/sim_models | Eddie Hung | 2019-09-18 | 2 | -7/+162 |
| | |\ | | | | | | | Added simulation models for Efinix and Anlogic | ||||
| | | * | make note that it is for latch mode | Miodrag Milanovic | 2019-09-18 | 1 | -0/+1 |
| | | | | |||||
| | | * | better lut handling | Miodrag Milanovic | 2019-09-18 | 1 | -4/+14 |
| | | | | |||||
| | | * | better handling of lut and begin/end add | Miodrag Milanovic | 2019-09-18 | 1 | -4/+10 |
| | | | | |||||
| | | * | Added simulation models for Efinix and Anlogic | Miodrag Milanovic | 2019-09-15 | 2 | -3/+141 |
| | | | | |||||
| | * | | xilinx: Make blackbox library family-dependent. | Marcin Kościelnicki | 2019-09-15 | 7 | -1024/+19252 |
| | |/ | | | | | | | Fixes #1246. | ||||
| * | | Fix copy-paste | Eddie Hung | 2019-09-18 | 1 | -2/+2 |
| | | | |||||
| * | | Mis-spell | Eddie Hung | 2019-09-18 | 1 | -10/+25 |
| | | | |||||
| * | | Add pattern detection support for DSP48E1 model, check against vendor | Eddie Hung | 2019-09-18 | 3 | -8/+102 |
| | | | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |