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* synth_xilinx -arch -> -family, consistent with older synth_intelEddie Hung2019-06-271-7/+8
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* Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymuxEddie Hung2019-06-272-12/+34
|\ | | | | synth_xilinx: Add -nocarry and -nowidelut options
| * GrrrEddie Hung2019-06-261-2/+2
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| * Fix spacingEddie Hung2019-06-261-5/+5
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| * Oops. Actually use nocarry flag as spotted by @koriakinEddie Hung2019-06-261-5/+7
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| * synth_ecp5 rename -nomux to -nowidelut, but preserve formerEddie Hung2019-06-261-6/+6
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| * Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into ↵Eddie Hung2019-06-261-4/+24
| |\ | | | | | | | | | koriakin/xc7nocarrymux
| | * synth_xilinx: Add -nocarry and -nomux options.Marcin Kościelnicki2019-04-301-7/+26
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* | | Simulation model verilog fixMiodrag Milanovic2019-06-262-14/+1
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* | | Add more ECP5 Diamond flip-flops.whitequark2019-06-262-30/+91
|/ / | | | | | | | | This includes all I/O registers, and a few more regular FFs where it was convenient.
* | Add RAM32X1D supportEddie Hung2019-06-245-20/+73
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* | ecp5: Improve mapping of $alu when BI is usedDavid Shah2019-06-211-4/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
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* | Fixed the help summary line for a few commandsacw12512019-06-191-1/+1
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* | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
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* | Merge pull request #1073 from whitequark/ecp5-diamond-iobDavid Shah2019-06-061-0/+15
|\ \ | | | | | | ECP5: implement most Diamond I/O buffer primitives
| * | ECP5: implement all Diamond I/O buffer primitives.whitequark2019-06-061-0/+15
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* | | Remove extra newlineEddie Hung2019-06-031-1/+0
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* | | Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
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* | | Add "min bits" and "min wports" to xilinx dram rulesEddie Hung2019-05-231-0/+4
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* | | Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-2/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | ice40/cells_sim.v: Add support for TRIM input to SB_HFOSCSylvain Munaut2019-05-131-0/+11
|/ / | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| | | | | | | | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-036-178/+124
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| * | Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
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| * | Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-032-0/+4
| |\ \ | | | | | | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| | * | Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-302-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
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| * | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-013-170/+104
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| | * \ \ Merge pull request #966 from YosysHQ/clifford/fix956Clifford Wolf2019-04-301-1/+1
| | |\ \ \ | | | | | | | | | | | | Drive dangling wires with init attr with their init value
| | | * | | Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-301-1/+1
| | | |/ / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
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| | * | | Cleanup ice40Eddie Hung2019-04-261-4/+6
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| * | | WIPEddie Hung2019-04-281-36/+22
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| * | | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
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| * | | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
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| * | Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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* | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-70/+70
| | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update help messageEddie Hung2019-04-221-1/+1
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* Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
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* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-2212-21/+480
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| * Merge pull request #941 from Wren6991/sim_lib_io_clkeClifford Wolf2019-04-221-10/+19
| |\ | | | | | | ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
| | * ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵Luke Wren2019-04-211-10/+19
| | | | | | | | | | | | experiments
| * | Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-masterClifford Wolf2019-04-2210-10/+458
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