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| * | | Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
| | | | | | | | | | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.
| * | | Vivado does not like zero width port connectionsEddie Hung2019-09-231-2/+2
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| * | | Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
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| * | | Add a xilinx_finalise passEddie Hung2019-09-233-0/+87
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| * | | GrammarEddie Hung2019-09-201-1/+1
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| * | | Fix signedness bugEddie Hung2019-09-201-2/+2
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| * | | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-202-3/+2
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| * | | Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
| | | | | | | | | | | | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab.
| * | | Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
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| * | | Tidy up, fix undrivenEddie Hung2019-09-191-32/+34
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| * | | $__ABC_REG to have WIDTH parameterEddie Hung2019-09-192-17/+18
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| * | | Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-194-349/+363
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| * | | Revert "Different approach to timing"Eddie Hung2019-09-194-195/+405
| | | | | | | | | | | | | | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044.
| * | | Different approach to timingEddie Hung2019-09-194-405/+195
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| * | | Suppress $anyseq warningsEddie Hung2019-09-191-15/+32
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| * | | Use (* techmap_autopurge *) to suppress techmap warningsEddie Hung2019-09-192-94/+99
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| * | | D is 25 bits not 24 bits wideEddie Hung2019-09-191-1/+1
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| * | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-198-90/+502
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| * | | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2Eddie Hung2019-09-191-1/+4
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| * | | | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
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| * | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-189-948/+19414
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| * | | | | Fix copy-pasteEddie Hung2019-09-181-2/+2
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| * | | | | Mis-spellEddie Hung2019-09-181-10/+25
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| * | | | | Add pattern detection support for DSP48E1 model, check against vendorEddie Hung2019-09-183-8/+102
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| * | | | | Add `undef DSP48E1_INSTEddie Hung2019-09-131-4/+5
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| * | | | | Fix D -> P{,COUT} delayEddie Hung2019-09-131-43/+43
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| * | | | | Add no MULT no DPORT configEddie Hung2019-09-134-226/+471
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| * | | | | Add support for MULT and DPORTEddie Hung2019-09-134-10/+588
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| * | | | | Refine diagramEddie Hung2019-09-131-12/+14
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| * | | | | Add an ASCII drawingEddie Hung2019-09-121-3/+22
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| * | | | | Finish explanationEddie Hung2019-09-122-5/+20
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| * | | | | Rename to techmap_guardEddie Hung2019-09-121-2/+3
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| * | | | | Initial DSP48E1 box supportEddie Hung2019-09-124-0/+867
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| * | | | | Set more ports explicitlyEddie Hung2019-09-121-1/+2
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| * | | | | Missing spaceEddie Hung2019-09-111-0/+1
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-115-53/+219
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| * | | | | | Move "(skip if -nodsp)" message to labelEddie Hung2019-09-101-4/+4
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| * | | | | | Be sensitive to signednessEddie Hung2019-09-101-20/+21
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| * | | | | | Really get rid of 'opt_expr -fine' by being explicitEddie Hung2019-09-102-9/+33
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| * | | | | | Remove wreduce callEddie Hung2019-09-101-1/+0
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| * | | | | | Add comment for why opt_expr is necessaryEddie Hung2019-09-101-0/+2
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| * | | | | | Revert "Remove "opt_expr -fine" call"Eddie Hung2019-09-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bfda921d0317bfb4cb6fc9de8a556c2258b709bc.
| * | | | | | Rename label to map_dspEddie Hung2019-09-101-1/+1
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| * | | | | | Remove "opt_expr -fine" callEddie Hung2019-09-101-1/+0
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| * | | | | | Set USE_MULT and USE_SIMDEddie Hung2019-09-091-1/+3
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| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-0520-91/+531
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-042-7/+8
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-308-120/+170
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| * \ \ \ \ \ \ \ Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-3034-384/+1864
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| | * \ \ \ \ \ \ \ Merge branch 'master' into xc7dspDavid Shah2019-08-3044-564/+1942
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