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* xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| | | Fixes #1225.
* xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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* Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-032-112/+270
|\ | | | | Gowin: add and test DFF init values
| * Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
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| * attempt to fix formattingPepijn de Vos2019-11-251-154/+154
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| * gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
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* | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
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* | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
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* | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
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* | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-251-2/+6
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* coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
| | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at>
* gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-198-43/+547
|\ | | | | Improvements for gowin support
| * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | | | | | | | | | The hardware does not actually support it. In reality it is always initialised to its reset value.
| * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
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| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-164-15/+439
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
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| * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1122-22988/+30572
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| * | | fix wide lutsPepijn de Vos2019-11-061-12/+12
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| * | | add IOBUFPepijn de Vos2019-10-282-1/+10
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| * | | add tristate buffer and testPepijn de Vos2019-10-282-2/+8
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| * | | More formattingPepijn de Vos2019-10-281-55/+49
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| * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
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| * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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| * | | add wide lutsPepijn de Vos2019-10-283-36/+119
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| * | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
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| * | | ALU sim tweaksPepijn de Vos2019-10-241-11/+11
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| * | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
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| * | | add negedge DFFPepijn de Vos2019-10-212-15/+139
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| * | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
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| * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-2158-1315/+24105
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| * | | | remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
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| * | | | Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
| * | | | fix BRAM width and initPepijn de Vos2019-09-062-12/+28
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| * | | | add more DFF to sim libPepijn de Vos2019-09-062-6/+111
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| * | | | WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
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| * | | | support bram initialisationPepijn de Vos2019-09-055-3/+25
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| * | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
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| * | | | add MUX supportPepijn de Vos2019-09-053-0/+17
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| * | | | set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
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| * | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| | * | | | Updating gowinDiego H2019-09-022-2/+2
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| * | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
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* | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
* | | | | ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
|\ \ \ \ \ | | | | | | | | | | | | Add "autoname" pass and use it in "synth_ice40"
| * | | | | Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
|\ \ \ \ \ \ | |/ / / / / |/| | | | | ice40: Support for post-place-and-route timing simulations
| * | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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