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| author | Diego H <diego@symbioticeda.com> | 2019-09-02 17:43:27 -0500 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-09-02 17:43:27 -0500 |
| commit | 5aa8d7ceeb663be24c7b815822d0de2ee25431a6 (patch) | |
| tree | b02a816b1d1fb0b9c144d50d9f54fa2a4329aaf9 /techlibs | |
| parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
| download | yosys-5aa8d7ceeb663be24c7b815822d0de2ee25431a6.tar.gz yosys-5aa8d7ceeb663be24c7b815822d0de2ee25431a6.tar.bz2 yosys-5aa8d7ceeb663be24c7b815822d0de2ee25431a6.zip | |
Updating gowin
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/gowin/arith_map.v | 2 | ||||
| -rw-r--r-- | techlibs/gowin/synth_gowin.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index e15de6423..af805b254 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - ALU #(.ALU_MODE(32'b0)) + ALU #(.ALU_MODE(0)) alu(.I0(AA[i]), .I1(BB[i]), .I3(1'b0), diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index ac3dbfb29..1fc029e3c 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -226,7 +226,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("vout")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s", + run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "<file-name>" : vout_file.c_str())); } } |