| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Allow initial blocks to be disabled during tests | Patrick Urban | 2021-11-13 | 1 | -1/+7 |
| | | | | | Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail. | ||||
| * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 1 | -11/+11 |
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| * | Unify verilog style | Miodrag Milanovic | 2019-10-18 | 1 | -7/+2 |
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| * | Share common tests | Miodrag Milanovic | 2019-10-18 | 1 | -0/+16 |
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index : iCE40/yosys | |
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