iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix FIRRTL to Verilog process instance subfield assignment.	Jim Lawson	2019-02-25	1	-1/+0
*	Append (instead of over-writing) EXTRA_FLAGS	Jim Lawson	2019-02-15	1	-1/+1
*	Update cells supported for verilog to FIRRTL conversion.	Jim Lawson	2019-02-15	1	-0/+24
*	Remove asicworld tests for (unsupported) switch-level modelling	Clifford Wolf	2019-01-27	4	-69/+0
*	Add optional SEED=n command line option to Makefile, and -S n command line op...	Eric Smith	2016-09-22	1	-1/+13
*	Some fixes in tests/asicworld/*_tb.v	Clifford Wolf	2016-05-20	4	-50/+41
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-1/+1
*	Fixed CRLF line endings	Clifford Wolf	2015-08-13	4	-266/+266
*	Some ASCII encoding fixes (comments and docs) by Larry Doolittle	Clifford Wolf	2015-08-13	1	-1/+1
*	Some test related fixes	Clifford Wolf	2015-02-12	3	-150/+0
*	Added autotest -e (do not use -noexpr on write_verilog)	Clifford Wolf	2014-08-30	1	-1/+1
*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30	1	-1/+1
*	Added note to "make test": use git checkout of iverilog	Clifford Wolf	2014-07-16	1	-1/+1
*	Added tests/realmath to "make test"	Clifford Wolf	2014-06-15	1	-1/+0
*	Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v	Clifford Wolf	2013-05-24	1	-1/+3
*	added more .gitignore files (make test)	Clifford Wolf	2013-01-05	1	-0/+2
*	initial import	Clifford Wolf	2013-01-05	89	-0/+2899