aboutsummaryrefslogtreecommitdiffstats
path: root/tests
Commit message (Collapse)AuthorAgeFilesLines
...
| | | * Fix div_mod testSergey2019-10-171-1/+1
| | | |
| | | * Fix div_mod testSergey2019-10-171-1/+1
| | | |
| | | * Fix div_mod testSergey2019-10-171-1/+1
| | | |
| | | * Fix div_mod testSergey2019-10-171-1/+1
| | | |
| | | * Fix div_mod testSergey2019-10-171-1/+1
| | | |
| | | * Fix div_mod testSergey2019-10-171-1/+1
| | | |
| | | * Add comment with expected behavior for latches,tribuf tests;Update adffs testSergeyDegtyar2019-10-174-14/+11
| | | |
| | | * Fix latches.ys testSergeyDegtyar2019-10-171-4/+3
| | | |
| | | * Remove xilinx_ug901 tests (will be moved to yosys-tests)SergeyDegtyar2019-10-1788-2962/+0
| | | |
| | | * Add smoke tests to tests/xilinxSergeyDegtyar2019-10-1729-9/+654
| | | |
| | | * Add comments for unproven cells.SergeyDegtyar2019-10-173-2/+3
| | | |
| | | * Add tests for Xilinx UG901 examplesSergeyDegtyar2019-10-1788-0/+2961
| | | |
| | | * Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-1410-0/+125
| | | |\ | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | | * sv: Improve testsDavid Shah2019-10-038-7/+30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | | * sv: Add test scripts for typedefsDavid Shah2019-10-034-0/+30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | | * sv: Add support for memories of a typedefDavid Shah2019-10-031-0/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | | * sv: Add support for memory typedefsDavid Shah2019-10-031-0/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | | * sv: Fix typedefs in packagesDavid Shah2019-10-031-0/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | | * sv: Fix typedef parametersDavid Shah2019-10-032-3/+22
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | | * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-0/+22
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * | Revert "Add test that is expecting to fail"Eddie Hung2019-10-081-20/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit c28d4b804720c2cf0086e921748219150e9631b5.
| | | * | Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-082-2/+60
| | | |\ \ | | | | | | | | | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming
| | | | * | Use `sat -tempinduct` and comments for why equiv_opt not sufficientEddie Hung2019-10-031-1/+8
| | | | | |
| | | | * | Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-021-2/+2
| | | | | |
| | | | * | Fix testEddie Hung2019-10-021-2/+12
| | | | | |
| | | | * | Merge branch 'eddie/fix_sat_init' into eddie/fix1427Eddie Hung2019-10-021-0/+20
| | | | |\ \
| | | | | * | Add test that is expecting to failEddie Hung2019-10-021-0/+20
| | | | | | |
| | | | * | | Update testEddie Hung2019-10-021-13/+3
| | | | | | |
| | | | * | | Add testEddie Hung2019-10-021-0/+31
| | | | |/ /
| | | * | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2syncEddie Hung2019-10-082-9/+4
| | | |\ \ \ | | | | | | | | | | | | | | async2sync to be called by equiv_opt only when -async2sync given
| | | | * | | Disable equiv check for ice40 latchesEddie Hung2019-10-031-6/+3
| | | | | | |
| | | | * | | Use equiv_opt -async2sync for xilinxEddie Hung2019-10-031-3/+1
| | | | |/ /
| | | * | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-051-0/+22
| | | | | |
| | * | | | hierarchy - proc reorderMiodrag Milanovic2019-10-189-14/+18
| | | | | |
| | * | | | Check latches type one by oneMiodrag Milanovic2019-10-042-40/+25
| | | | | |
| | * | | | Removed top module where not neededMiodrag Milanovic2019-10-044-37/+4
| | | | | |
| | * | | | Test muxes synth one by oneMiodrag Milanovic2019-10-042-38/+39
| | | | | |
| | * | | | Cleaned verilog code from not used definesMiodrag Milanovic2019-10-041-6/+0
| | | | | |
| | * | | | Check for MULT18X18D, since that is working nowMiodrag Milanovic2019-10-042-14/+11
| | | | | |
| | * | | | Check flops one by oneMiodrag Milanovic2019-10-044-71/+50
| | | | | |
| | * | | | Removed alu and div_mod tests as agreedMiodrag Milanovic2019-10-044-57/+0
| | | | | |
| | * | | | equiv_opt with -assertEddie Hung2019-09-301-3/+1
| | | | | |
| | * | | | Update resource count for alu.ysEddie Hung2019-09-301-3/+3
| | | | | |
| | * | | | Move $x to end as per 7f0eec8Eddie Hung2019-09-301-1/+1
| | | | | |
| | * | | | Update fsm.ys resource countEddie Hung2019-09-301-3/+3
| | | | | |
| | * | | | Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys ↵Eddie Hung2019-09-3036-0/+800
| | |\ \ \ \ | | | |_|/ / | | |/| | | | | | | | | into eddie/pr1352
| | | * | | Add comment to dpram test about related issue.SergeyDegtyar2019-09-181-0/+1
| | | | | |
| | | * | | adffs test update (equiv_opt -multiclock). div_mod test fixSergeyDegtyar2019-09-173-17/+12
| | | | | |
| | | * | | Remove stat command form shifter.ys testSergeyDegtyar2019-09-041-1/+1
| | | | | |
| | | * | | Fix ecp5 testsSergeyDegtyar2019-09-0411-2421/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 02:54:03 +0000