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* sv: fix up end label checkingZachary Snow2021-06-166-0/+80
| | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
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* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-097-79/+79
|\ | | | | Fixing old e-mail addresses and deadnames
| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-091-1/+1
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| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-0/+11
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-083-0/+52
|/ | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-012-0/+34
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* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-311-0/+100
| | | | Fixes #2775.
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* verilog: fix case expression sign and width handlingZachary Snow2021-05-252-0/+108
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* sv: support remaining assignment operatorsZachary Snow2021-05-251-0/+23
| | | | | - Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+47
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* opt_mem_feedback: Rewrite feedback path finding logic.Marcelina Kościelnicka2021-05-242-0/+243
| | | | Fixes #2766.
* Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-231-0/+17
| | | | Fixes #1854.
* opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-231-0/+34
| | | | Fixes #2765.
* tests/blif: Add missing gitignoreMarcelina Kościelnicka2021-05-201-0/+1
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* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* sv: check validity of package end labelZachary Snow2021-05-101-0/+15
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* blif: Use library cells' start_offset and upto for wideports.Marcelina Kościelnicka2021-05-082-0/+26
| | | | Fixes #2729.
* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-041-8/+13
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* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+1
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* quicklogic: ABC9 synthesisLofty2021-04-176-17/+17
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* preproc: test coverage for #2712Zachary Snow2021-03-303-0/+18
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* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-291-1/+56
| | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-293-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
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* verilog: check entire user type stack for type definitionXiretza2021-03-211-0/+10
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* sv: allow typenames as function return typesZachary Snow2021-03-192-0/+40
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* quicklogic: PolarPro 3 supportLofty2021-03-1810-0/+262
| | | | | | | | Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* sv: carry over global typedefs from previous filesZachary Snow2021-03-172-0/+60
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-0/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* blackbox: Include whiteboxed modulesgatecat2021-03-171-0/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-0/+29
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* proc_arst: Add special-casing of clock signal in conditionals.Marcelina Kościelnicka2021-03-151-0/+31
| | | | | | | | | | | | | | | | | The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656.
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-151-11/+20
| | | | Fixes #2546.
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-151-0/+14
| | | | | | | | | Among other problems, this also fixes equality comparisons between SigSpec by enforcing a canonical form. Also fix another minor issue with possible non-canonical SigSpec. Fixes #2623.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-0/+20
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+16
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-082-2/+1
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* proc_dff: Fix emitted FF when a register is not assigned in async resetMarcelina Kościelnicka2021-03-081-0/+23
| | | | Fixes #2619.
* tests/bram: Do not generate write address collisions.Marcelina Kościelnicka2021-03-081-5/+23
| | | | These have no defined semantics, making the tests non-deterministic.
* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-0710-0/+177
|\ | | | | sv: support for parameters without default values
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