#!/usr/bin/env python
#
# Copyright 2008, Google Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
#     * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
#     * Redistributions in binary form must reproduce the above
# copyright notice, this list of conditions and the following disclaimer
# in the documentation and/or other materials provided with the
# distribution.
#     * Neither the name of Google Inc. nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

"""Tests the text output of Google C++ Mocking Framework.

SYNOPSIS
       gmock_output_test.py --build_dir=BUILD/DIR --gengolden
         # where BUILD/DIR contains the built gmock_output_test_ file.
       gmock_output_test.py --gengolden
       gmock_output_test.py
"""

__author__ = 'wan@google.com (Zhanyong Wan)'

import os
import re
import sys

import gmock_test_utils


# The flag for generating the golden file
GENGOLDEN_FLAG = '--gengolden'

PROGRAM_PATH = gmock_test_utils.GetTestExecutablePath('gmock_output_test_')
COMMAND = [PROGRAM_PATH, '--gtest_stack_trace_depth=0', '--gtest_print_time=0']
GOLDEN_NAME = 'gmock_output_test_golden.txt'
GOLDEN_PATH = os.path.join(gmock_test_utils.GetSourceDir(), pre { line-height: 125%; margin: 0; }
td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight { background: #ffffff; }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *  
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *  
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#ifndef SIGTOOLS_H
#define SIGTOOLS_H

#include "kernel/rtlil.h"
#include "kernel/log.h"
#include <assert.h>
#include <set>

struct SigPool
{
	typedef std::pair<RTLIL::Wire*,int> bitDef_t;
	std::set<bitDef_t> bits;

	void clear()
	{
		bits.clear();
	}

	void add(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			bits.insert(bit);
		}
	}

	void add(const SigPool &other)
	{
		for (auto &bit : other.bits)
			bits.insert(bit);
	}

	void del(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			bits.erase(bit);
		}
	}

	void del(const SigPool &other)
	{
		for (auto &bit : other.bits)
			bits.erase(bit);
	}

	void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
	{
		from.expand();
		to.expand();
		assert(from.chunks.size() == to.chunks.size());
		for (size_t i = 0; i < from.chunks.size(); i++) {
			bitDef_t bit_from(from.chunks[i].wire, from.chunks[i].offset);
			bitDef_t bit_to(to.chunks[i].wire, to.chunks[i].offset);
			if (bit_from.first == NULL || bit_to.first == NULL)
				continue;
			if (bits.count(bit_from) > 0)
				bits.insert(bit_to);
		}
	}

	RTLIL::SigSpec extract(RTLIL::SigSpec sig)
	{
		RTLIL::SigSpec result;
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			bitDef_t bit(c.wire, c.offset);
			if (bits.count(bit) > 0)
				result.append(c);
		}
		return result;
	}

	RTLIL::SigSpec remove(RTLIL::SigSpec sig)
	{
		RTLIL::SigSpec result;
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			bitDef_t bit(c.wire, c.offset);
			if (bits.count(bit) == 0)
				result.append(c);
		}
		return result;
	}

	bool check_any(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			bitDef_t bit(c.wire, c.offset);
			if (bits.count(bit) != 0)
				return true;
		}
		return false;
	}

	bool check_all(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			bitDef_t bit(c.wire, c.offset);
			if (bits.count(bit) == 0)
				return false;
		}
		return true;
	}

	RTLIL::SigSpec export_one()
	{
		RTLIL::SigSpec sig;
		for (auto &bit : bits) {
			sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
			break;
		}
		return sig;
	}

	RTLIL::SigSpec export_all()
	{
		RTLIL::SigSpec sig;
		for (auto &bit : bits)
			sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
		sig.sort_and_unify();
		return sig;
	}

	size_t size()
	{
		return bits.size();
	}
};

template <typename T, class Compare = std::less<T>>
struct SigSet
{
	typedef std::pair<RTLIL::Wire*,int> bitDef_t;
	std::map<bitDef_t, std::set<T, Compare>> bits;

	void clear()
	{
		bits.clear();
	}

	void insert(RTLIL::SigSpec sig, T data)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			bits[bit].insert(data);
		}
	}

	void insert(RTLIL::SigSpec sig, const std::set<T> &data)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			bits[bit].insert(data.begin(), data.end());
		}
	}

	void erase(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			bits[bit].clear();
		}
	}

	void erase(RTLIL::SigSpec sig, T data)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			bits[bit].erase(data);
		}
	}

	void erase(RTLIL::SigSpec sig, const std::set<T> &data)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			bits[bit].erase(data.begin(), data.end());
		}
	}

	void find(RTLIL::SigSpec sig, std::set<T> &result)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			for (auto &data : bits[bit])
				result.insert(data);
		}
	}

	std::set<T> find(RTLIL::SigSpec sig)
	{
		std::set<T> result;
		find(sig, result);
		return result;
	}

	bool has(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (auto &c : sig.chunks) {
			if (c.wire == NULL)
				continue;
			assert(c.width == 1);
			bitDef_t bit(c.wire, c.offset);
			if (bits.count(bit))
				return true;
		}
		return false;
	}
};

struct SigMap
{
	typedef std::pair<RTLIL::Wire*,int> bitDef_t;

	struct shared_bit_data_t {
		RTLIL::SigChunk chunk;
		std::set<bitDef_t> bits;
	};

	std::map<bitDef_t, shared_bit_data_t*> bits;

	SigMap(RTLIL::Module *module = NULL)
	{
		if (module != NULL)
			set(module);
	}

	SigMap(const SigMap &other)
	{
		copy(other);
	}

	const SigMap &operator=(const SigMap &other)
	{
		copy(other);
		return *this;
	}

	void copy(const SigMap &other)
	{
		clear();
		for (auto &bit : other.bits) {
			bits[bit.first] = new shared_bit_data_t;
			bits[bit.first]->chunk = bit.second->chunk;
			bits[bit.first]->bits = bit.second->bits;
		}
	}

	void swap(SigMap &other)
	{
		bits.swap(other.bits);
	}

	~SigMap()
	{
		clear();
	}

	void clear()
	{
		std::set<shared_bit_data_t*> all_bd_ptr;
		for (auto &it : bits)
			all_bd_ptr.insert(it.second);
		for (auto bd_ptr : all_bd_ptr)
			delete bd_ptr;
		bits.clear();
	}

	void set(RTLIL::Module *module)
	{
		clear();
		for (auto &it : module->connections)
			add(it.first, it.second);
	}

	// internal helper function
	void register_bit(const RTLIL::SigChunk &c)
	{
		assert(c.width == 1);
		bitDef_t bit(c.wire, c.offset);
		if (c.wire && bits.count(bit) == 0) {
			shared_bit_data_t *bd = new shared_bit_data_t;
			bd->chunk = c;
			bd->bits.insert(bit);
			bits[bit] = bd;
		}
	}

	// internal helper function
	void unregister_bit(const RTLIL::SigChunk &c)
	{
		assert(c.width == 1);
		bitDef_t bit(c.wire, c.offset);
		if (c.wire && bits.count(bit) > 0) {
			shared_bit_data_t *bd = bits[bit];
			bd->bits.erase(bit);
			if (bd->bits.size() == 0)
				delete bd;
			bits.erase(bit);
		}
	}

	// internal helper function
	void merge_bit(const RTLIL::SigChunk &c1, const RTLIL::SigChunk &c2)
	{
		assert(c1.wire != NULL && c2.wire != NULL);
		assert(c1.width == 1 && c2.width == 1);

		bitDef_t b1(c1.wire, c1.offset);
		bitDef_t b2(c2.wire, c2.offset);

		shared_bit_data_t *bd1 = bits[b1];
		shared_bit_data_t *bd2 = bits[b2];
		assert(bd1 != NULL && bd2 != NULL);

		if (bd1 == bd2)
			return;

		if (bd1->bits.size() < bd2->bits.size())
		{
			for (auto &bit : bd1->bits)
				bits[bit] = bd2;
			bd2->bits.insert(bd1->bits.begin(), bd1->bits.end());
			delete bd1;
		}
		else
		{
			bd1->chunk = bd2->chunk;
			for (auto &bit : bd2->bits)
				bits[bit] = bd1;
			bd1->bits.insert(bd2->bits.begin(), bd2->bits.end());
			delete bd2;
		}
	}

	// internal helper function
	void set_bit(const RTLIL::SigChunk &c1, const RTLIL::SigChunk &c2)
	{
		assert(c1.wire != NULL);
		assert(c1.width == 1 && c2.width == 1);
		bitDef_t bit(c1.wire, c1.offset);
		assert(bits.count(bit) > 0);
		bits[bit]->chunk = c2;
	}

	// internal helper function
	void map_bit(RTLIL::SigChunk &c)
	{
		assert(c.width == 1);
		bitDef_t bit(c.wire, c.offset);
		if (c.wire && bits.count(bit) > 0)
			c = bits[bit]->chunk;
	}

	void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
	{
		from.expand();
		to.expand();

		assert(from.chunks.size() == to.chunks.size());
		for (size_t i = 0; i < from.chunks.size(); i++)
		{
			RTLIL::SigChunk &cf = from.chunks[i];
			RTLIL::SigChunk &ct = to.chunks[i];

			if (cf.wire == NULL)
				continue;

			register_bit(cf);
			register_bit(ct);

			if (ct.wire != NULL)
				merge_bit(cf, ct);
			else
				set_bit(cf, ct);
		}
	}

	void add(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (size_t i = 0; i < sig.chunks.size(); i++)
		{
			RTLIL::SigChunk &c = sig.chunks[i];
			if (c.wire != NULL) {
				register_bit(c);
				set_bit(c, c);
			}
		}
	}

	void del(RTLIL::SigSpec sig)
	{
		sig.expand();
		for (auto &c : sig.chunks)
			unregister_bit(c);
	}

	void apply(RTLIL::SigSpec &sig)
	{
		sig.expand();
		for (auto &c : sig.chunks)
			map_bit(c);
		sig.optimize();
	}

	RTLIL::SigSpec operator()(RTLIL::SigSpec sig)
	{
		apply(sig);
		return sig;
	}
};

#endif /* SIGTOOLS_H */