module test ( input EN, CLK, input [3:0] D, output reg [3:0] Q ); always @(posedge CLK) if (EN) Q <= D; specify `ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); `endif endspecify endmodule module test2 ( input A, B, output Q ); xor (Q, A, B); specify //specparam T_rise = 1; //specparam T_fall = 2; `define T_rise 1 `define T_fall 2 (A => Q) = (`T_rise,`T_fall); //(B => Q) = (`T_rise+`T_fall)/2.0; (B => Q) = 1.5; endspecify endmodule module issue01144(input clk, d, output q); specify (posedge clk => (q +: d)) = (3,1); (posedge clk *> (q +: d)) = (3,1); endspecify endmodule lass='main'>index : iCE40/yosys clone of https://github.com/YosysHQ/yosys

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module test1(a, b, c, d, e, f, y);
    input [19:0] a, b, c;
    input [15:0] d, e, f;
    output [41:0] y;
    assign y = a*b + c*d + e*f;
endmodule

module test2(a, b, c, d, e, f, y);
    input [19:0] a, b, c;
    input [15:0] d, e, f;
    output [41:0] y;
    assign y = a*b + (c*d + e*f);
endmodule